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PDF IS61QDB41M36 Data sheet ( Hoja de datos )
| Número de pieza | IS61QDB41M36 | |
| Descripción | 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs | |
| Fabricantes | ISSI | |
| Logotipo |  |
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36 Mb (1M x 36. & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI®
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Separate read and write ports with concurrent
read and write operations.
• Synchronous pipeline read with late write opera-
tion.
• Double data rate (DDR) interface for read and
write input ports.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
May 2005
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb IS61QDB41M36 and
IS61QDB42M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
• Read/write address
• Read enable
• Write enable
• Byte writes for burst addresses 1 and 3
• Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle after the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
During the burst read operation, the data-outs from
the first and third bursts are updated from output
registers off the second and fourth rising edges of
the C clock (starting 1.5 cycles later). The data-outs
from the second and fourth bursts are updated with
the third and fifth rising edges of the C clock. The K
and K clocks are used to time the data-outs when-
ever the C and C clocks are tied high. Two full clock
cycles are required to complete a read operation
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
1
Free Datasheet http://www.datasheetlist.com/
1 page  
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI®
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into
the array on the third write cycle. A read cycle to the last two write addresses produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see X18/X36 Write Truth Tables on page 10 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 16. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never
be connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock
mode to minimize power and requires only 1024 cycles to restart.
No clocks can be issued until VDD reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differ-
ential clocks
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.
In the following application example, the second pair of C and C clocks is delayed such that the return data
meets the data setup and hold times at the bus master.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
5
Free Datasheet http://www.datasheetlist.com/
5 Page 
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI®
X18 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 9.
Operation
K(t+1) K(t+1.5) K(t+2) K(t+2.5) BW0 BW1
DB
DB+1
DB+2
DB+3
Write Byte 0 L→H
LH
D0-8 (t+1)
Write Byte 1 L→H
HL
D9-17 (t+1)
Write All Bytes L→H
L L D0-17 (t+1)
Abort Write L→H
HH
Don’t care
Write Byte 0
L→H
LH
D0-8 (t+1.5)
Write Byte 1
L→H
HL
D9-17 (t+1.5)
Write All Bytes
L→H
LL
D0-17 (t+1.5)
Abort Write
L→H
HH
Don’t care
Write Byte 0
L→H
LH
D0-8 (t+2)
Write Byte 1
L→H
HL
D9-17 (t+2)
Write All Bytes
L→H
LL
D0-17 (t+2)
Abort Write
L→H
HH
Don’t care
Write Byte 0
L→H L H
D0-8 (t+2.5)
Write Byte 1
L→H H
L
D9-17 (t+2.5)
Write All Bytes
L→H L
L
D0-17 (t+2.5)
Abort Write
L→H H H
Don’t care
Notes;
1. For all cases. W needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Characteristics on page 17. Signals must have AC specifications with respect to switching
clocks K and K.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
11
Free Datasheet http://www.datasheetlist.com/
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet IS61QDB41M36.PDF ] | |
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