PDF IS65WV102416BLL Data sheet ( Hoja de datos )

Número de pieza	IS65WV102416BLL
Descripción	1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES • High-speed access times: 25, 35 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CS1 and OE options • CS1 power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply VDD 1.65V to 2.2V (IS62WV102416ALL) speed = 35ns for VDD 1.65V to 2.2V VDD 2.4V to 3.6V (IS62/65WV102416BLL) speed = 25ns for VDD 2.4V to 3.6V • Packages available: – 48-ball miniBGA (9mm x 11mm) – 48-pin TSOP (Type I) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes DESCRIPTION The ISSIIS62WV102416ALL/BLL and IS65WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-perform- ance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 1 Free Datasheet http://www.datasheetlist.com/ 1 page IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL OPERATING RANGE (VDD) (IS62WV102416ALL) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C VDD (35 nS) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (VDD) (IS62WV102416BLL)(1) Range Ambient Temperature VDD (25 nS) Commercial 0°C to +70°C 2.4V-3.6V Industrial –40°C to +85°C 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. OPERATING RANGE (VDD) (IS65WV102416BLL) Range Ambient Temperature Automotive –40°C to +125°C VDD (25 nS) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 5 Free Datasheet http://www.datasheetlist.com/ 5 Page IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter tWC Write Cycle Time tSCS1/tSCS2 CS1/CS2 to Write End tAW Address Setup Time to Write End tHA Address Hold from Write End tSA Address Setup Time tPWB LB, UB Valid to End of Write tPWE(4) WE Pulse Width tSD Data Setup to Write End tHD Data Hold from Write End tHZWE(3) WE LOW to High-Z Output tLZWE(3) WE HIGH to Low-Z Output 25ns Min. Max. 25 — 18 — 15 — 0— 0— 18 — 18 — 12 — 0— — 12 5— 35 ns Min. Max. 35 — 25 — 25 — 0— 0— 25 — 30 — 15 — 0— — 20 5— Unit ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof 0.4toVDD-0.2V/0.4VtoVDD-0.3Vand outputloadingspecifiedinFigure1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested. 4. tPWE > tHZWE + tSD when OE is LOW. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) ADDRESS CS1 CS2 WE LB, UB DOUT DIN tWC tSCS1 tHA tSCS2 tAW tPWE tPWB tSA tHZWE DATA UNDEFINED HIGH-Z tLZWE tSD tHD DATA-IN VALID Notes: 1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1,CS2andWEinputsandatleastoneoftheLBandUBinputs beingintheLOWstate. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 11 Free Datasheet http://www.datasheetlist.com/ 11 Page

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