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89170MのメーカーはSanyo Semicon Deviceです、この部品の機能は「 LC89170M」です。 |
部品番号 | 89170M |
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部品説明 | LC89170M | ||
メーカ | Sanyo Semicon Device | ||
ロゴ | |||
このページの下部にプレビューと89170Mダウンロード(pdfファイル)リンクがあります。 Total 8 pages
Ordering number : EN*5536A
CMOS LSI
LC89170M
CD Player Text Data IC
Preliminary
Overview
The LC89170M is an IC that decodes the text data, such
as song names, stored in subcode channels R to W of a
compact disk’s read-in area.
Features
• Accepts the channel R to W subcode data through a
subcode interface.
• Can continuously output the channel R to W data for
each 1PACK24 symbol.
• Performs error detection (cyclic redundancy code) and
outputs both the data and the result of that check.
• Provides synchronization protection for the subcode
interface.
• Supports low-voltage operation (3.3 V)
• Provided in the miniature MFP-14S package.
Package Dimensions
unit: mm
3111-MFP14S
[LC89170M]
SANYO: MFP14S
Specifications
Absolute Maximum Ratings at Ta = 25 °C, VSS = 0 V
Parameter
Maximum supply voltage
I/O voltages
Input current
Operating temperature
Storage temperature
Symbol
VDD max
VI VO
II
Topr
Tstg
Conditions
Recommended Operating Conditions at Ta = 25 °C, VSS = 0 V
Parameter
Supply voltage
Operating temperature
Symbol
VDD
Topr
Conditions
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
±10
–30 to +70
–55 to +125
Unit
V
V
mA
°C
°C
Ratings
Unit
min typ max
3.0 5.0 5.5 V
–30 +70 V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
93096HA (OT) No. 5536-1/8
Free Datasheet http://www.datasheetlist.com/
1 Page LC89170M
DC Characteristics
DC Characteristics (1) at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter
Symbol
Conditions
Input high-level voltage
CMOS compatible; 1*
VIH CMOS compatible Schmitt; 2*
Input low-level voltage
CMOS compatible; 1*
VIL CMOS compatible Schmitt; 2*
Output high-level voltage VOH IOH = –2 mA; 3*
Output low-level voltage
VOL IOH = 2 mA; 3*
Current drain
IDD
VDD = 5 V, Ta = 25°C, MCK = 16.93 MHz
VDD = 5 V, XMODE = [L]
Note: 1. The MCK, TEST, SW1, and SW2 pins
2. The EXCK, SBSO, SCOR, WFCK, XMODE, and SCLK pins
3. The EXCK, SRDT, and DQSY pins
min
0.7 VDD
0.8 VDD
VDD–2.1
Ratings
typ
0.8
60
max
0.3 VDD
0.2 VDD
0.4
1.6
120
Unit
V
V
V
V
V
V
mA
µA
DC Characteristics (2) at Ta = –30 to +70°C, VDD = 3.0 to 3.6 V, VSS = 0 V
Parameter
Symbol
Conditions
Input high-level voltage
CMOS compatible; 1*
VIH CMOS compatible Schmitt; 2*
Input low-level voltage
CMOS compatible; 1*
VIL CMOS compatible Schmitt; 2*
Output high-level voltage VOH IOH = –1 mA; 3*
Output low-level voltage
VOL IOH = 1 mA; 3*
Current drain
IDD
VDD = 3.3 V, Ta = 25°C, MCK = 16.93 MHz
VDD = 3.3 V, XMODE = [L]
Note: 1. The MCK, TEST, SW1, and SW2 pins
2. The EXCK, SBSO, SCOR, WFCK, XMODE, and SCLK pins
3. The EXCK, SRDT, and DQSY pins
AC Characteristics
• The MCK pin
AC Characteristics (1) at Ta = –30 to +70°C, VDD = 3.0 to 5.5 V, VSS = 0 V
Parameter
High-level pulse width
Low-level pulse width
Pulse period
Rise and fall times
Symbol
tWH
tWL
tC
tR, tF
Conditions
min
0.7 VDD
0.75 VDD
VDD–0.8
Ratings
typ
max
0.2 VDD
0.15 VDD
0.4
0.5 1.0
25 50
Ratings
min typ max
25 56
25 56
58 100
12
Unit
V
V
V
V
V
V
mA
µA
Unit
ns
ns
ns
ns
No. 5536-3/8
Free Datasheet http://www.datasheetlist.com/
3Pages LC89170M
The EXCK clock characteristics are determined by SW2 as listed in the table below.
EXCK Clock Selection by SW2
SW1
SW2
tCD
tWH
tWL Unit
12.28
1.89
1.89
µs
[L] [L]
208TMCK
32TMCK
32TMCK
µs
18.90
7.56
7.56
µs
[L] [H]
320TMCK
128TMCK
128TMCK
µs
The upper boxes assume MCK = 16.934 MHz
The lower boxes indicate the relationship with MCK (TMCK = 1/MCK)
• Microcontroller interface
The LC89170M includes a 32-word × 8-bit dual-port RAM on chip, and the 1PACK 24 symbols from subcode channels
R to W can be read out once every 3.3 ms (or once every 1.66 for double-speed playback) over the microcontroller
interface. Figure 3 shows the timing.
Figure 3 Microcontroller Interface Output Timing
The 1PACK 24 symbols for the subcode R to W data (18 bytes) are entered into the dual-port RAM and input to the CRC
checking circuit. After the data for 1 PACK has all been input, a falling edge is output from the DQSY pin and the CRC
flags are output from SRDT. A high is output for the CRC flags if the check returned OK. Next, 128 bits of data are
output by inputting the SCLK clock signal. A single packet of data is output by repeating this operation four times.
No. 5536-6/8
Free Datasheet http://www.datasheetlist.com/
6 Page | |||
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部品番号 | 部品説明 | メーカ |
89170M | LC89170M | Sanyo Semicon Device |