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PDF HEF4526B Data sheet ( Hoja de datos )

Número de pieza HEF4526B
Descripción Programmable 4-bit binary down counter
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! HEF4526B Hoja de datos, Descripción, Manual

HEF4526B
Programmable 4-bit binary down counter
Rev. 5 — 22 November 2011
Product data sheet
1. General description
The HEF4526B is a synchronous programmable 4-bit binary down counter with active
HIGH and active LOW clock inputs (CP0, CP1), an asynchronous parallel load input (PL),
four parallel inputs (A0 to A3), a cascade feedback input (CF), four buffered parallel
outputs (Q0 to Q3), a terminal count output (TC), an overriding asynchronous master
reset input (MR) and a decoded TC output that can be used for divide-by-n applications.
In single stage applications the TC output is connected to PL. CF allows cascade
divide-by-n operation with no additional gates required.
Information on A0 to A3 is loaded into the counter while PL is HIGH, independent of all
other inputs except MR, which must be LOW. When PL and CP1 are LOW, the counter
advances on a LOW-to-HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the
counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in
the zero state (Q0 = Q1 = Q2 = Q3 = LOW) and CF is HIGH and PL is LOW. A HIGH on
MR resets the counter (Q0 to Q3 = LOW) independent of other inputs. The clock input is
highly tolerant of slower clock rise and fall times due to Schmitt trigger action.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
Description
HEF4526BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4526BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1

1 page




HEF4526B pdf
NXP Semiconductors
HEF4526B
Programmable 4-bit binary down counter
6. Functional description
Table 3. Function table[1]
MR PL
CP0 CP1 Mode
H X X X reset (asynchronous)
L H X X preset (asynchronous)
L L H no change
L L L no change
L L X no change
L L X no change
L L L counter advances
L L H counter advances
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition.
Table 4. Counting mode
CF = HIGH; PL = LOW; MR = LOW.
Count
Outputs
Q3 Q2 Q1 Q0
15 H H H H
14 H H H L
13 H H L
H
12 H H L
L
11 H
L
HH
10 H
L
HL
9 HL L H
8 HL L L
7 L HHH
6 L HHL
5 L HL H
4 L HL L
3 L L HH
2 L L HL
1LLLH
0LLLL
HEF4526B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 22 November 2011
© NXP B.V. 2011. All rights reserved.
5 of 19

5 Page





HEF4526B arduino
NXP Semiconductors
11. Waveforms
HEF4526B
Programmable 4-bit binary down counter
Vl
CP0
input
0V
Vl
CP1
input
0V
VOH
Qn
output
VOL
VOH
TC
output
VOL
1/fmax
VM
tW
VM
tPLH
VM
tPLH
VM
tW
tPHL
tPHL
tPLH
001aae724
a. Propagation delays for CP0, CP1 to Qn, and TC, minimum CP0 and CP1 pulse widths and maximum frequency
Vl
PL input
VM
0V
tsu tW th
Vl
An input
VM
0V
VOH
Qn output
VOL
tPLH
90%
10%
tt
tPHL
tt
001aae723
b. Propagation delays for PL and An to Qn, setup and hold times for PL to An, Qn transition times and minimum PL
pulse width
Fig 6.
Measurement points are given in Table 11.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Waveforms showing switching times
HEF4526B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 22 November 2011
© NXP B.V. 2011. All rights reserved.
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