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HEF4071B の電気的特性と機能

HEF4071BのメーカーはNXP Semiconductorsです、この部品の機能は「Quadruple 2-input OR gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 HEF4071B
部品説明 Quadruple 2-input OR gate
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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HEF4071B Datasheet, HEF4071B PDF,ピン配置, 機能
HEF4071B
Quad 2-input OR gate
Rev. 8 — 16 December 2015
Product data sheet
1. General description
The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise
immunity and pattern insensitivity to output impedance variations.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
Specified from 40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C.
Type number
Package
Name
Description
HEF4071BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT108-1
4. Functional diagram
 $
 %
 $
 %
 $
 %
 $
 %
< 
< 
< 
< 
DDM
Fig 1. Functional diagram
Q$
Q%
Q<
DDM
Fig 2. Logic diagram (one gate)

1 Page





HEF4071B pdf, ピン配列
NXP Semiconductors
HEF4071B
Quad 2-input OR gate
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min Max Unit
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb = 40 C to + 125 C
SO14
0.5 +18 V
- 10 mA
0.5 VDD + 0.5 V
- 10 mA
- 10 mA
- 50 mA
65 +150 C
40 +125 C
[1] -
500 mW
P power dissipation
per output
- 100 mW
[1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VDD
VI
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
input transition rise and fall rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Max Unit
3 15 V
0 VDD V
40 +125 C
- 3.75 s/V
- 0.5 s/V
- 0.08 s/V
HEF4071B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 16 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 11


3Pages


HEF4071B 電子部品, 半導体
NXP Semiconductors
11. Waveforms
HEF4071B
Quad 2-input OR gate
9,
Q$Q%LQSXW
9 
WU

90
W3/+
92+
Q<RXWSXW
92/


90
W7/+
WI
W3+/
W7+/
DDL
Fig 4.
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Input to output propagation delay and output transition times
Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
9''
9,
*
'87
92
57 &/
DDJ
Fig 5.
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
5 V to 15 V
Input
VI
VSS or VDD
tr, tf
20 ns
Load
CL
50 pF
HEF4071B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 16 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 11

6 Page



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部品番号部品説明メーカ
HEF4071B

Quadruple 2-input OR gate

NXP Semiconductors
NXP Semiconductors
HEF4071B

Quadruple 2-input OR gate

Philips
Philips


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