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PDF HEF4053B Data sheet ( Hoja de datos )
| Número de pieza | HEF4053B | |
| Descripción | Triple 2-channel analogue multiplexer/demultiplexer | |
| Fabricantes | NXP Semiconductors | |
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HEF4053B
Triple single-pole double-throw analog switch
Rev. 11 — 11 September 2014
Product data sheet
1. General description
The HEF4053B is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input
(Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All
three switches share an enable input (E). A HIGH on E causes all switches into the
high-impedance OFF-state, independent of Sn.
VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E).
The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C.
Type number Package
Name
Description
HEF4053BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4053BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
HEF4053BTT TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT403-1
1 page  
NXP Semiconductors
HEF4053B
Triple single-pole double-throw analog switch
Table 5.
Symbol
t/V
Recommended operating conditions …continued
Parameter
Conditions
input transition rise and fall
rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Typ Max Unit
- - 3.75 s/V
- - 0.5 s/V
- - 0.08 s/V
15
VDD − VSS
(V)
10
001aae646
operating area
5
0
0 5 10 15
VDD − VEE (V)
Fig 7. Operating area as a function of the supply voltages
10. Static characteristics
Table 6. Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions
VDD Tamb = 40 C Tamb = 25 C
Min Max Min Max
Tamb = 85 C
Min Max
Tamb = 125 C Unit
Min Max
VIH HIGH-level IO < 1 A
input voltage
5V
10 V
3.5 - 3.5 - 3.5 - 3.5 - V
7.0 - 7.0 - 7.0 - 7.0 - V
15 V
11.0 - 11.0 - 11.0 - 11.0 - V
VIL
LOW-level
IO < 1 A
input voltage
5V
10 V
- 1.5 - 1.5 - 1.5 - 1.5 V
- 3.0 - 3.0 - 3.0 - 3.0 V
15 V
- 4.0 - 4.0 - 4.0 - 4.0 V
II input leakage
current
15 V
- 0.1 - 0.1 - 1.0 - 1.0 A
IS(OFF)
OFF-state
leakage
current
Z port;
15 V
all channels OFF;
see Figure 8
- - - 1000 - - - - nA
Y port;
per channel;
see Figure 9
15 V
- - - 200 - - - - nA
HEF4053B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 20
5 Page 
NXP Semiconductors
HEF4053B
Triple single-pole double-throw analog switch
11.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
VSS = VEE = 0 V; Tamb = 25 C.
Symbol
THD
Parameter
total harmonic distortion
Conditions
see Figure 16; RL = 10 k; CL = 15 pF;
channel ON; VI = 0.5VDD (p-p);
fi = 1 kHz
VDD
5V
10 V
15 V
f(3dB)
3 dB frequency response see Figure 17; RL = 1 k; CL = 5 pF;
channel ON; VI = 0.5VDD (p-p)
5V
10 V
15 V
iso
isolation (OFF-state)
see Figure 18; fi = 1 MHz; RL = 1 k; 10 V
CL = 5 pF; channel OFF;
VI = 0.5VDD (p-p)
Vct crosstalk voltage digital inputs to switch; see Figure 19; 10 V
RL = 10 k; CL = 15 pF;
E or Sn = VDD (square-wave)
Xtalk
crosstalk
between switches; see Figure 20;
fi = 1 MHz; RL = 1 k;
VI = 0.5VDD (p-p)
10 V
[1] fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).
Typ
[1] 0.25
[1] 0.04
[1] 0.04
[1] 13
[1] 40
[1] 70
[1] 50
Max
-
-
-
-
-
-
-
Unit
%
%
%
MHz
MHz
MHz
dB
50 -
mV
[1] 50
- dB
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 2500 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 11500 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 29000 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
11.2.1 Test circuits
VDD
VDD or VSS
VSS
S1 to S3
nZ
E
nY0 1
nY1 2
switch
VSS = VEE
RL
fi
CL D
001aaj904
Fig 16. Test circuit for measuring total harmonic
distortion
VDD
VDD or VSS
VSS
S1 to S3
nZ
E
nY0 1
nY1 2
switch
VSS = VEE
RL
fi
CL dB
001aaj905
Fig 17. Test circuit for measuring frequency response
HEF4053B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 20
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