PDF HEF4017B Data sheet ( Hoja de datos )

Número de pieza	HEF4017B
Descripción	5-stage Johnson decade counter
Fabricantes	NXP Semiconductors
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No Preview Available ! HEF4017B 5-stage Johnson decade counter Rev. 9 — 8 April 2016 Product data sheet 1. General description The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0, CP1). Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits  Automatic counter correction  Tolerant of slow clock rise and fall times  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specified from 40 C to +125 C  Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number Package Name Description HEF4017BT SO16 plastic small outline package; 16 leads; body width 3.9 mm Version SOT109-1 1 page NXP Semiconductors &3,1387 &3,1387 05,1387 4287387 4287387 4287387 4287387 4287387 4287387 4287387 4287387 4287387 4287387 4287387 Fig 6. Timing diagram HEF4017B 5-stage Johnson decade counter DDK HEF4017B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 8 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 18 5 Page NXP Semiconductors HEF4017B 5-stage Johnson decade counter 9, &3LQSXW 966 9, &3LQSXW 966 9, 05LQSXW 966 92+ 44 RXWSXW 92/ 92+ 444 RXWSXW 92/ IPD[ W: 90 IPD[ 90 90 W: WUHF W: 90 W3+/ 90 W3/+ DDM Fig 8. Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, tW and trec are measured when CP0 = HIGH and CP1 triggers on a HIGH-to-LOW transition. The shaded areas indicate where the output state is set by the input count. Measurement points given in Table 9. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays 9, &3LQSXW 966 9, &3LQSXW 966 90 WK 90 90 WK 90 DDH Fig 9. Hold times are shown as positive values, but may be specified as negative values; Measurement points given in Table 9. Waveforms showing hold times for CP0 to CP1 and CP1 to CP0 Table 9. Measurement points Supply voltage VDD 5 V to 15 V Input VM 0.5VDD Output VM 0.5VDD HEF4017B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 8 April 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 11 of 18 11 Page

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