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HEF4011UBのメーカーはNXP Semiconductorsです、この部品の機能は「Quadruple 2-input NAND gate」です。 |
部品番号 | HEF4011UB |
| |
部品説明 | Quadruple 2-input NAND gate | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューとHEF4011UBダウンロード(pdfファイル)リンクがあります。 Total 8 pages
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4011UB
gates
Quadruple 2-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
1 Page Philips Semiconductors
Quadruple 2-input NAND gate
Product specification
HEF4011UB
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL TYP. MAX.
Propagation delays
In → On
HIGH to LOW
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
Input capacitance
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
CIN
60 120
25 50
20 40
35 70
20 40
17 35
75 150
30 60
20 40
60 110
30 60
20 40
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
TYPICAL EXTRAPOLATION
FORMULA
25 ns + (0,70 ns/pF) CL
12 ns + (0,27 ns/pF) CL
10 ns + (0,20 ns/pF) CL
8 ns + (0,55 ns/pF) CL
9 ns + (0,23 ns/pF) CL
9 ns + (0,16 ns/pF) CL
15 ns + (1,20 ns/pF) CL
6 ns + (0,48 ns/pF) CL
4 ns + (0,32 ns/pF) CL
10 ns + (1,00 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
500 fi + ∑ (foCL) × VDD2
where
10
5 000 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
25 000 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
3Pages Philips Semiconductors
Quadruple 2-input NAND gate
Product specification
HEF4011UB
gates
APPLICATION INFORMATION
Some examples of applications for the HEF4011UB are shown below.
Because of the fact that this circuit is unbuffered, it is suitable for use in (partly) analogue circuits.
INH O
LH
H OSC
In Fig.9 the oscillation frequency is mainly determined by R1C1,
provided R1 << R2 and R2C2 << R1C1.
The function of R2 is to minimize the influence of the forward voltage
across the protection diodes on the frequency; C2 is a stray (parasitic)
capacitance. The period Tp is given by Tp = T1 + T2, in which
T1
=
R1C1
In
V-----D---D-----+-----V----S---T-- a n d
VST
T2
=
R1C1
In
-2---V-----D---D-----–----V-----S---T-
VDD – VST
where
VST is the signal threshold level of the gate. The period is fairly
independent of VDD, VST and temperature. The duty factor, however, is
influenced by VST.
Fig.9 (a) Astable relaxation oscillator using two HEF4011UB gates; the diodes may be BAW62; C2 is a parasitic
capacitance.
(b) Waveforms at the points marked A, B, C and D in the circuit diagram.
January 1995
6
6 Page | |||
ページ | 合計 : 8 ページ | ||
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PDF ダウンロード | [ HEF4011UB データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
HEF4011UB | Quadruple 2-input NAND gate | NXP Semiconductors |