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HEF4011B の電気的特性と機能

HEF4011BのメーカーはNXP Semiconductorsです、この部品の機能は「Quadruple 2-input NAND gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 HEF4011B
部品説明 Quadruple 2-input NAND gate
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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HEF4011B Datasheet, HEF4011B PDF,ピン配置, 機能
HEF4011B
Quad 2-input NAND gate
Rev. 5 — 21 November 2011
Product data sheet
1. General description
The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the
highest noise immunity and pattern insensitivity to output impedance.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
Inputs and outputs are protected against electrostatic effects
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number Package
Name Description
HEF4011BP DIP14 plastic dual in-line package; 14 leads (300 mil)
HEF4011BT SO14 plastic small outline package; 14 leads; body width 3.9 mm
4. Functional diagram
Version
SOT27-1
SOT108-1
1A 1
1B 2
2A 5
2B 6
3A 8
3B 9
4A 12
4B 13
3 1Y
4 2Y
10 3Y
11 4Y
001aan874
Fig 1. Functional diagram
nA
nB
nY
001aan875
Fig 2. Logic diagram (one gate)

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HEF4011B pdf, ピン配列
NXP Semiconductors
HEF4011B
Quad 2-input NAND gate
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min Max
Unit
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb = 40 C to + 125 C
DIP14
0.5
-
0.5
-
-
-
65
40
[1] -
+18
10
VDD + 0.5
10
10
50
+150
+125
V
mA
V
mA
mA
mA
C
C
750 mW
SO14
[2] -
500 mW
P power dissipation
per output
- 100 mW
[1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K.
[2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
VDD
VI
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
input transition rise and fall rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Typ Max
Unit
3 - 15 V
0-
40 -
VDD
+125
V
C
- - 3.75 s/V
- - 0.5 s/V
- - 0.08 s/V
HEF4011B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
3 of 12


3Pages


HEF4011B 電子部品, 半導体
NXP Semiconductors
11. Waveforms
HEF4011B
Quad 2-input NAND gate
VI
input
10 %
0V
tr
90 %
VM
tPHL
VOH
output
VOL
90 %
VM
10 %
tTHL
tf
tPLH
tTLH
001aag197
Fig 4.
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Propagation delay, output transition time
Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
VI
G
VDD
DUT
RT
VO
CL
001aag182
Fig 5.
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
5 V to 15 V
Input
VI
VSS or VDD
tr, tf
20 ns
Load
CL
50 pF
HEF4011B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
6 of 12

6 Page



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