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Datasheet HI-8282APJI PDF ( 特性, スペック, ピン接続図 )

部品番号 HI-8282APJI
部品説明 ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
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HI-8282APJI Datasheet, HI-8282APJI PDF,ピン配置, 機能
May 2001
HI-8282A
ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
GENERAL DESCRIPTION
The HI-8282A is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The transmitter
section provides the ARINC 429 communication protocol.
Additional interface circuitry such as the Holt HI-8585,
HI-8586 or HI-3182 is required to translate the 5 volt logic
outputs to ARINC 429 drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8282A examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
FEATURES
! ARINC specification 429 compatible
! 16-Bit parallel data bus
! Direct receiver interface to ARINC bus
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
! Parity functions
! Low power, single 5 volt supply
! Industrial & full military temperature ranges
PIN CONFIGURATION (Top View)
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-8282APQI
&
HI-8282APQT
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 - 429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional Package Pin Configurations)
(DS8282A Rev. New)
HOLT INTEGRATED CIRCUITS
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05/01

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HI-8282APJI pdf, ピン配列
HI-8282A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8282A contains 10 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS FUNCTION CONTROL
PIN
DESCRIPTION
BDO5
If enabled, an internal connection
SELF TEST 0 = ENABLE is made passing 429DO and
429DO to the receiver logic inputs
RECEIVER 1
BDO6 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
If Receiver 1 Decoder is
- enabled, the ARINC bit 9
must match this bit
BDO8
-
If Receiver 1 Decoder is
- enabled, the ARINC bit 10
must match this bit
RECEIVER 2
BDO9 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BD10
-
If Receiver 2 Decoder is
- enabled, then ARINC bit 9
must match this bit
BD11
-
If Receiver 2 Decoder is
- enabled, then ARINC bit 10
must match this bit
BD12
INVERT
XMTR
PARITY
Logic 0 enables normal odd parity
1 = ENABLE and Logic 1 enables even parity
output in transmitter 32nd bit
BD13 XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14 RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
BIT
BYTE 2
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BIT
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8282A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13v signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-8282APJI 電子部品, 半導体
HI-8282A
REPEATER OPERATION
The repeater mode of operation allows a data word that has been
received by the HI-8282A to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into the receiver
shift register, the D/R flag will go low. A logic "0" is placed on the SEL
line and EN is strobed. This is the same procedure as for normal
receiver operation and it places the lower byte (16) of the data word
on the data bus. By strobing PL1 at the same time as EN, the byte
will also be placed into the transmitter FIFO. SEL is then taken high
and EN is strobed again to place the upper byte of the data word on
the data bus. By strobing PL2 at the same time as EN, the second
byte will also be placed into the FIFO. The data word is now ready to
be transmitted according to the parity programmed into the control
word register.
In normal operation, either byte of a received data word may be read
from the receiver latches first by use of SEL input. During repeater
operation however, the lower byte of the data word must be read
first. This is necessary because, as the data is being read, it is also
being loaded into the FIFO and the transmitter FIFO is always
loaded with the lower byte of the data word first.
429DO
429DO
ARINC BIT
DATA
NULL
BIT 30
DATA
NULL
BIT 31
DATA
NULL
BIT 32
WORD GAP
BIT 1
NEXT WORD
DATA BUS
CWSTR
VALID
tCWSET
tCWHLD
tCWSTR
DATA BUS
tD/R
tSELEN
tD/REN
tENDATA
tEND/R
tENSEL
tEN
tSELEN
tENSEL
BYTE 1 VALID
tENEN
tDATAEN
tENDATA
BYTE 2 VALID
tDATAEN
HOLT INTEGRATED CIRCUITS
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