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K9GAG08U0F の電気的特性と機能

K9GAG08U0FのメーカーはSamsungです、この部品の機能は「16Gb F-die NAND Flash」です。


製品の詳細 ( Datasheet PDF )

部品番号 K9GAG08U0F
部品説明 16Gb F-die NAND Flash
メーカ Samsung
ロゴ Samsung ロゴ 




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K9GAG08U0F Datasheet, K9GAG08U0F PDF,ピン配置, 機能
Rev.1.1, May. 2011
K9GAG08U0F
16Gb F-die NAND Flash
Multi-Level-Cell (2bit/cell)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2011 Samsung Electronics Co., Ltd. All rights reserved.
-1-
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1 Page





K9GAG08U0F pdf, ピン配列
K9GAG08U0F
datasheet
Rev. 1.1
FLASH MEMORY
Table Of Contents
1.0 INTRODUCTION ........................................................................................................................................................ 5
1.1 Features .................................................................................................................................................................. 5
1.2 Product List.............................................................................................................................................................. 5
1.3 General Description................................................................................................................................................. 5
1.4 Pin Configuration (48TSOP) .................................................................................................................................... 6
1.4.1Package Dimensions ......................................................................................................................................... 6
1.5 Pin Description ........................................................................................................................................................ 7
2.0 PRODUCT INTRODUCTION...................................................................................................................................... 10
2.1 Absolute Maximum Ratings ..................................................................................................................................... 11
2.2 Recommended Operating Conditions ..................................................................................................................... 11
2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.) ................................... 11
2.4 Valid Block............................................................................................................................................................... 12
2.5 AC Test Condition ................................................................................................................................................... 12
2.6 Capacitance(TA=25°C, VCC=3.3V, f=1MHz) .......................................................................................................... 12
2.7 Mode Selection........................................................................................................................................................ 12
2.8 Program / Erase Characteristics.............................................................................................................................. 13
2.9 AC Timing Characteristics for Command / Address / Data Input ........................................................................... 13
2.10 AC Characteristics for Operation........................................................................................................................... 14
3.0 NAND FLASH TECHNICAL NOTES .......................................................................................................................... 15
3.1 Initial Invalid Block(s) ............................................................................................................................................... 15
3.2 Identifying Initial Invalid Block(s) ............................................................................................................................. 15
3.3 Error In Write or Read Operation............................................................................................................................. 16
3.4 Addressing For Program Operation......................................................................................................................... 18
3.5 System Interface Using CE don’t-care. ................................................................................................................... 20
4.0 TIMING DIAGRAMS ................................................................................................................................................... 21
4.1 Command Latch Cycle ............................................................................................................................................ 21
4.2 Address Latch Cycle................................................................................................................................................ 21
4.3 Input Data Latch Cycle ............................................................................................................................................ 22
4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)...................................................................................... 22
4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) ..................................................................... 23
4.6 Status Read Cycle .................................................................................................................................................. 23
4.7 Read Operation ...................................................................................................................................................... 24
4.8 Read Operation(Intercepted by CE) ....................................................................................................................... 24
4.9 Random Data Output In a Page ............................................................................................................................. 25
4.10 Cache Read Operation......................................................................................................................................... 26
4.11 Two-Plane Page Read Operation with Two-Plane Random Data Out ................................................................. 27
4.12 Two-Plane Cache Read Operation with Two-Plane Random Data Out (1/2)....................................................... 28
4.13 Two-Plane Cache Read Operation with Two-Plane Random Data Out (2/2)....................................................... 29
4.14 Page Program Operation...................................................................................................................................... 29
4.15 Page Program Operation with Random Data Input .............................................................................................. 30
4.16 Copy-Back Program Operation with Random Data Input ..................................................................................... 31
4.17 Intelligent Copy-Back Program(1/2) ..................................................................................................................... 32
4.18 Cache Program Operation(available only within a block) ..................................................................................... 34
4.19 Two-Plane Copy-Back Program ............................................................................................................................ 35
4.20 Two-Plane Intelligent Copy-Back Program(1/3) .................................................................................................... 36
4.21 Two-Plane Page Program Operation .................................................................................................................... 39
4.22 Two-Plane Cache Program Operation ................................................................................................................ 40
4.23 Block Erase Operation.......................................................................................................................................... 41
4.24 Two-Plane Block Erase Operation ....................................................................................................................... 42
4.25 Read ID Operation................................................................................................................................................ 43
4.26 00h Address ID Cycle............................................................................................................................................ 43
4.27 40h Address ID Cycle............................................................................................................................................ 43
5.0 DEVICE OPERATION ................................................................................................................................................ 46
5.1 Page Read.............................................................................................................................................................. 46
5.2 Cache Read............................................................................................................................................................ 47
5.3 Two-plane Page Read............................................................................................................................................. 49
5.4 Two-plane Cache Read .......................................................................................................................................... 50
5.5 Page Program ......................................................................................................................................................... 51
5.6 Copy-back Program................................................................................................................................................ 52
-3-
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3Pages


K9GAG08U0F 電子部品, 半導体
K9GAG08U0F
datasheet
Rev. 1.1
FLASH MEMORY
1.4 Pin Configuration (48TSOP)
K9GAG08U0F-SCB0
Vcc
Vss
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
Vss
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48 Vss
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 VccQ
37 Vcc
36 Vss
35 N.C
34 VccQ
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 Vss
1.4.1 Package Dimensions
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
20.00±0.20
0.787±0.008
#1 #48
Unit :mm/Inch
#24
0~8°
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
#25
1.00±0.05
0.039±0.002
01..02407MAX
0.05
0.002
MIN
(
0.50
0.020
)
-6-
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6 Page



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共有リンク

Link :


部品番号部品説明メーカ
K9GAG08U0D

FLASH MEMORY

Samsung
Samsung
K9GAG08U0E

16Gb E-die NAND Flash

Samsung
Samsung
K9GAG08U0F

16Gb F-die NAND Flash

Samsung
Samsung
K9GAG08U0M

Flash Memory

Samsung
Samsung


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