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PDF AR9223 Data sheet ( Hoja de datos )
| Número de pieza | AR9223 | |
| Descripción | Single-Chip 2x2 MIMO MAC/BB/Radio | |
| Fabricantes | Atheros | |
| Logotipo |  |
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Data Sheet
October 2009
AR9223 Single-Chip 2x2 MIMO MAC/BB/Radio with PCI
Interface for 802.11n 2.4 GHz WLANs
General Description
The Atheros AR9223 is a highly integrated
single-chip solution for 2.4 GHz 802.11n-ready
wireless local area networks (WLANs) that
enables high-performance 2x2 MIMO
configurations for wireless station applications
demanding robust link quality and maximum
throughput and range. The AR9223 integrates a
multi-protocol MAC, baseband processor,
analog-to-digital and digital-to-analog (ADC/
DAC) converters, 2x2 MIMO radio transceiver,
and PCI interface in an all-CMOS device for low
power and small form factor applications.
The AR9223 implements half-duplex OFDM,
CCK, and DSSS baseband processing, supporting
up to 130 Mbps for 20 MHz and 300 Mbps for
40 MHz channel operations respectively, and
IEEE 802.11b/g data rates. Additional features
include signal detection, automatic gain control,
frequency offset estimation, symbol timing, and
channel estimation. The AR9223 MAC supports
the 802.11 wireless MAC protocol, 802.11i
security, receive and transmit filtering, error
recovery, and quality of service (QoS).
The AR9223 supports two simultaneous traffic
streams using up to two integrated transmit
chains and receive chains for high throughput
and range performance. Transmit chains combine
baseband in-phase (I) and quadrature (Q) signals,
convert them to the desired frequency, and drive
the RF signal to multiple antennas. he receiver
converts an RF signal to baseband I and Q
outputs. The frequency synthesizer supports
one-MHz steps to match frequencies defined by
IEEE 802.11b/g/n specifications.
The AR9223 supports frame data transfer to and
from the host using a PCI interface that provides
interrupt generation and reporting, power save,
and status reporting. Other external interfaces
include serial EEPROM and GPIOs. The AR9223
interoperates with standard legacy 802.11b/g
devices.
Features
■ All-CMOS MIMO solution interoperable with
IEEE 802.11b/g/n WLANs
■ 2x2 MIMO technology improves effective
throughput and range over existing
802.11b/g products
■ Supports spatial multiplexing, cyclic-delay
diversity (CDD), and maximal ratio
combining (MRC)
■ 2.4 GHz WLAN MAC/BB processing
■ BPSK, QPSK, 16 QAM, 64 QAM, DBPSK,
DQPSK, and CCK modulation schemes
■ Data rates of up to 130 Mbps for 20 MHz
channels and 300 Mbps for 40 MHz channels
■ Wireless multimedia enhancements quality of
service support (QoS)
■ 802.11e-compatible bursting
■ Support for IEEE 802.11e, h, and i standards
■ WEP, TKIP, and AES hardware encryption
■ 20 and 40 MHz channelization
■ 32-bit 0–33 and 66-MHz PCI 2.3 interface
■ Reduced (short) guard interval
■ Frame aggregation
■ Block ACK
■ IEEE 1149.1 standard test access port and
boundary scan architecture supported
■ 337-pin, 12 mm x 12 mm BGA package
AR9223 System Block Diagram
2.4 GHz
2x2
Radio
Front-
End
Circuits
Rx Radio BB Filters
Tx Radio in/out MUX
Rx Radio BB Filters
Tx Radio in/out MUX
Frequency Synthesizers
Bias/Control
DAC
ADC
DAC
ADC
Baseband
AR9223
MAC/
Configuration
Control/
Memory
Host and
Peripheral
Interface
40 MHz
Crystal
PCI
Serial EEPROM
GPIOs
© 2000-2009 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super
AG®, Super G®, Total 802.11n®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air
is Cleaner at 5-GHz™, XSPAN™, Wireless Future. Unleashed Now.™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
Free Datasheet http://www.datasheet-pdf.com/
1 page  
1. Pin Descriptions
This section contains a package pinout (see
Table 1-1, Table 1-2, and Table 1-3) and a
tabular listing of the signal descriptions.
This nomenclature is used for signal names:
NC No connection should be made to
this pin
_L At the end of the signal name,
indicates active low signals
P At the end of the signal name,
indicates the positive side of a
differential signal
N At the end of the signal name
indicates the negative side of a
differential signal
This nomenclature is used for signal types:
I Digital input signal
I/O A digital bidirectional signal
IA Analog input signal
IH Input signals with weak internal
pull-up, to prevent signals from
floating when left open
IL Input signals with weak internal
pull-down, to prevent signals
from floating when left open
O A digital output signal
OA An analog output signal
OD A digital output signal with open
drain
P A power or ground signal
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9223 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 5
October 2009 • 5
Free Datasheet http://www.datasheet-pdf.com/
5 Page 
Table 1-3. Signal-to-Pin Relationships and Descriptions (continued)
Symbol
Serial EEPROM
EPRM_SCK
EPRM_SDA
Pin Type Description
N23 O Serial EEPROM clock
N22 I/O Serial EEPROM data
Symbol
Power
AVDD12
AVDD12_XTAL
AVDD33
AVDD33_XTAL
DVDD12
DVDD33
GND
NC
Pin Description
A13, B3, B9, B16, C1, J2, N1
Analog 1.2 V power supply
B20 Supply voltage for the crystal
oscillator
A8, A16, B8, C2, H1, H2
Analog 3.3 V power supply
B21 Supply voltage for the crystal
oscillator
H23, T22, AA2, AB8, AB11, AB16
Digital 1.2 V power supply
H22, T2, T23, AB3, AB13, AB20, AC8
Digital 3.3 V power supply
A1, A3, A18, A19, A22, A23, B2, B5, B7, B10, B18, B19, B22, GND
B23, C23, D23, E2, E22, E23, F6, F7, F8, F9, F10, F11, F12,
F13, F14, F15, F16, F17, F18, G2, G6, G7, G8, G9, G10, G11,
G12, G13, G14, G15, G16, G17, G18, H6, H7, H8, H9, H10,
H11, H12, H13, H14, H15, H16, H17, H18, J6, J7, J8, J9, J10,
J11, J12, J13, J14, J15, J16, J17, J18, K2, K6, K7, K8, K9, K10,
K11, K12, K13, K14, K15, K16, K17, K18, L6, L7, L8, L9,
L10, L11, L12, L13, L14, L15, L16, L17, L18, M6, M7, M8,
M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, N6,
N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17,
N18, P2, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16,
P17, P18, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
R17, R18, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16,
T17, T18, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15,
U16, U17, U18, U22, V6, V7, V8, V9, V10, V11, V12, V13,
V14, V15, V16, V17, V18, AB2, AB22, AC1, AC4, AC23
A4, A5, A6, A7, A17, B4, B6, B17,C22, D22, J1, K1, L1, L2, No connect
M1, M2, P1, R1, R2, T1, AC3
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9223 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 11
October 2009 • 11
Free Datasheet http://www.datasheet-pdf.com/
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AR9223.PDF ] | |
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