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PDF BD9483FV Data sheet ( Hoja de datos )
| Número de pieza | BD9483FV | |
| Descripción | White LED Driver | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
LED Drivers for LCD Backlights
White LED Driver for large LCD
Panels (DCDC Converter type)
BD9483F,FV
●General Description
BD9483F,FV is a high efficiency driver for white LEDs
and designed for large LCDs. This IC is built-in 2ch
boost DCDC converters that employ an array of LEDs
as the light source. BD9483F,FV has some protect
function against fault conditions, such as the
over-voltage protection (OVP), the over current limit
protection of DCDC (OCP), Max duty protection, LED
OCP protection. Therefore BD9483F,FV is available for
the fail-safe design over a wide range output voltage.
●Key Specification
Operating power supply voltage range:11.0V to 35.0V
Oscillator frequency:
150kHz (RT=100kΩ)
Operating Current:
3mA (typ.)
Operating temperature range:
-40°C to +85°C
●Applications
TV, Computer Display, Notebook, LCD Backlighting
●Features
■ 2ch boost DCDC converter with current mode
■ LED protection circuit (Max duty protection, LED
OCP protection)
■ Over-voltage protection (OVP) for the output
voltage Vout
■ Adjustable soft start
■ The wide range of analog dimming 0.2V-3.0V
■ 2ch independent PWM dimming input
■ The UVLO detection for the input voltage of the
power stage
■ FAIL logic output
●Package
SOP-24:
Pin Pitch:
W(Typ.) D(Typ.) H(Max.)
15.00mm x 7.80mm x 2.01mm
1.27mm
●Typical Application Circuit
VCC
VIN
VOUT1
VOUT2
REG90
STB
RT
Css SS
Ccp CP
FAILB
PWM1
PWM2
ADIM
VCC
VREG
UVLO
VCC
UVLO
UVLO
TSD
OVP
OVP
REG90
UVLO
OSC
SS
SS-FB
clamper
Fail
detect
PWM
COMP
CONTROL
LOGIC
Current
compensation
REG90
GATE1
CS1
LEB
PGND1
REG90
DIMOUT1
MAXFB
LEDOCP
ERROR
amp
1.0V
ISENSE1
FB1
Each channel
GATE2
CS2
1/3 PGND2
DIMOUT2
ISENSE2
FB2
Figure 1. Typical Application Circuit
Figure 2-1. SOP-24
SSOP-B24:
Pin Pitch:
W(Typ.) D(Typ.) H(Max.)
7.80mm x 7.60mm x 1.35mm
0.65mm
Figure 2-2. SSOP-B24
○Product structure：Silicon monolithic integrated circuit
.www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product is not designed protection against radioactive rays
1/29
TSZ02201-0F1F0C100100-1-2
28.Nov.2013 Rev.003
Free Datasheet http://www.datasheet4u.net/
1 page  
BD9483F,FV
●1.3 Pin Descriptions
Pin No
Pin Name
1 VCC
2 STB
3 CS1
4 GATE1
5 GND1
6 DIMOUT1
7 ISENSE1
8 FB1
9 ADIM
10 PWM1
11 PWM2
12 FAILB
13 RT
14 OVP
15 SS
16 CP
17 UVLO
18 FB2
19 ISENSE2
20 DIMOUT2
21 GND2
22 GATE2
23 CS2
24 REG90
●1.4.1 Pin ESD Type1
OVP
Datasheet
In/Out
Function
- Power supply pin
In IC ON/OFF pin
In DC/DC output current detect pin for ch1,OCP input pin for ch1
Out DC/DC switching output pin for ch1
- Ground for ch1
Out Dimming signal output for NMOS for ch1
In Current detection input pin for ch1
Out Error amplifier output pin for ch1
In ADIM signal input-output pin
In External PWM dimming signal input pin ch1
In External PWM dimming signal input pin ch2
Out Abnormality detection output pin
Out For DC/DC switching frequency setting pin
In Over voltage protection detection pin
Out Slow start setting pin
Out Charge timer for abnormal state.
In Under voltage lock out detection pin
Out Error amplifier output pin for ch2
In Current detection input pin for ch2
Out Dimming signal output for NMOS for ch2
- Ground for ch2
Out DC/DC switching output pin for ch2
In DC/DC output current detect pin for ch2,OCP input pin for ch2
Out 9.0V output voltage
Rating
[V]
-0.3 to 36
-0.3 to 36
-0.3 to 7
-0.3 to 14
-
-0.3 to 14
-0.3 to 7
-0.3 to 7
-0.3 to 20
-0.3 to 20
-0.3 to 20
-0.3 to 36
-0.3 to 7
-0.3 to 20
-0.3 to 7
-0.3 to 7
-0.3 to 20
-0.3 to 7
-0.3 to 7
-0.3 to 14
-
-0.3 to 14
-0.3 to 7
-0.3 to 14
UVLO
SS
100k
5V
OVP
UVLO
50k
5V
RT PWM1 / PWM2
100k
5V
1M
PWMx
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
Figure 5. Pin ESD Type
5/29
ADIM
TSZ02201-0F1F0C100100-1-2
28.Nov.2013 Rev.003
Free Datasheet http://www.datasheet4u.net/
5 Page 
BD9483F,FV
Datasheet
Status
Normal
Abnormal
FAILB output
OPEN
GND Level
RT （13 PIN）
DC/DC switching frequency setting pin. RT set the oscillation frequency inside IC.
○The relationship between the frequency and RT resistance value (ideal)
R RT
15000
fSW [kHz]
[k Ω ]
The oscillation setting range from 50kHz to 800kHz.
The setting examples is separately described in the section ” ●3.4.4 how to set DCDC oscillation frequency”
OVP （14 PIN）
The OVP terminal is the input for over-voltage protection. As OVP is more than 3.0V, the over-voltage protection (OVP)
will work. At the moment of these detections, the BD9483F,FV stops the switching of the output GATE and starts to count
up the abnormal interval, but IC doesn't reach latch off state instantaneously until the detection continues up to 4 counts
of GATE terminals. (Please refer to the time chart 3.7.4)
As the latch off by OVP, both channels stop. (GATE1=GATE2=L, DIMOUT1=DIMOUT2=L)
The OVP pin is high impedance, because the internal resistance to a certain bias is not connected.
So, the bias by the external components is required, even if OVP function is not used, because the open connection of
this pin is not fixed the potential.
The setting examples is separately described in the section ”●3.4.6 how to set OVP”
SS （15 PIN）
The pin which sets soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to external
capacitance Css(0.001μF to 4.7μF). The switching duty of GATE output will be limited during 0V to 4.0V of the SS
voltage.
So the equality of the soft start interval can be expressed as following
Tss = 1.33*106*Css
Css: the external capacitance of the SS pin.
Regarding of the logic of SS=L
(SS=L) = (PWM1orPWM2 have not asserted H since ResetB=L->H) or (latch off state)
where ResetB = (STB=H) and (VCCUVLO=H) and (REG90UVLO=H)
Please refer to the time chart 3.7.3 on soft start behavior
CP （16 PIN）
Timer pin for counting the abnormal state of the FBMAX protection. If the abnormal state is detected, The CP pin start
charging by 3μA to the external capacitance. As the CP voltage reaches to 3.0V, IC will be latched off. In latch off both
channels will be stopped (GATE1=GATE2=L, DIMOUT1=DIMOUT2=L).
Please refer to the section “●3.4.7 how to set the interval until latch off (CP pin)” for more detail.
UVLO （17 PIN）
Under voltage lock out pin for the input voltage of the power stage. More than 3.0V(typ.), IC starts the boost operation
and stops lower than 2.8V(typ.).
The UVLO pin is high impedance, because the internal resistance to a certain bias is not connected.
So, the bias by the external components is required, even if UVLO function is not used, because the open connection of
this pin is not fixed the potential.
As the latch off by UVLO, both channels stop. (GATE1=GATE2=L, DIMOUT1=DIMOUT2=L)
The setting examples is separately described in the section ”●3.4.5 how to set UVLO”
REG90 （24 PIN）
This is the 9.0V (typ.) output pin that is used for the power supply of DIMOUT, GATE. Available current is 15mA (min.).
When VCC<11V , REG90 output voltage decreases because of the saturation.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/29
TSZ02201-0F1F0C100100-1-2
28.Nov.2013 Rev.003
Free Datasheet http://www.datasheet4u.net/
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet BD9483FV.PDF ] | |
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