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PDF AD9258 Data sheet ( Hoja de datos )
| Número de pieza | AD9258 | |
| Descripción | 1.8V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9258 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9258
FEATURES
SNR = 77.6 dBFS @ 70 MHz and 125 MSPS
SFDR = 88 dBc @ 70 MHz and 125 MSPS
Low power: 750 mW @ 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−152.8 dBm/Hz small signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO/ SCLK/
DCS DFS CSB
DRVDD
AD9258
SPI
VIN+A
VIN–A
ADC
PROGRAMMING DATA
CMOS/LVDS 14
OUTPUT BUFFER
ORA
D13A (MSB)
TO
D0A (LSB)
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
ADC
MULTICHIP
SYNC
DIVIDE 1
TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
CMOS/LVDS 14
OUTPUT BUFFER
CLK+
CLK–
DCOA
DCOB
ORB
D13B (MSB)
TO
D0B (LSB)
AGND SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5. Pin compatibility with the AD9268, allowing a simple
migration from 14 bits to 16 bits. The AD9258 is also pin
compatible with the AD9251, AD9231, and AD9204 family
of products for lower sample rate, low power applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
AD9258
Parameter
POWER CONSUMPTION
DC Input
Sine Wave Input1
(DRVDD = 1.8 V
CMOS Output
Mode)
Sine Wave Input1
(DRVDD = 1.8 V
LVDS Output
Mode)
Standby Power3
Power-Down Power
Temperature
Full
Full
Full
Full
Full
AD9258BCPZ-80
Min Typ
Max
462 487
481
568
45
0.5 2.5
AD9258BCPZ-105
Min Typ
Max
565 590
605
671
45
0.5 2.5
AD9258BCPZ-125
Min Typ
Max
750 777
797
865
45
0.5 2.5
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Unit
mW
mW
mW
mW
mW
Rev. A | Page 5 of 44
Free Datasheet http://www.datasheet4u.com/
5 Page 
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
tPD
CH A CH B
N – 12 N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N–9
CH B
N–9
CH A
N–8
Figure 4. LVDS Mode Data Output Timing
AD9258
CLK+
SYNC
tSSYNC
tHSYNC
Figure 5. SYNC Input Timing Requirements
Rev. A | Page 11 of 44
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9258.PDF ] | |
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