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9250-08 の電気的特性と機能

9250-08のメーカーはIntegrated Circuit Systemsです、この部品の機能は「 ICS9250-08」です。


製品の詳細 ( Datasheet PDF )

部品番号 9250-08
部品説明 ICS9250-08
メーカ Integrated Circuit Systems
ロゴ Integrated Circuit Systems ロゴ 




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9250-08 Datasheet, 9250-08 PDF,ピン配置, 機能
Integrated
Circuit
Systems, Inc.
ICS9250-08
Frequency Generator & Integrated Buffers for Celeron & PII/III
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
• 3 - CPUs @2.5V, up to 150MHz.
• 17 - SDRAM @ 3.3V, up to 150MHz.
• 7 - PCI @3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 150MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Key Specifications:
• CPU – CPU: <175ps
• CPU – PCI: min = 1ns max = 4ns
• PCI – PCI: <250ps
• SDRAM - SDRAM: <500ps
Block Diagram
Pin Configuration
VDDREF
*FS2/REF1
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
{I 2 C
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDLIOAPIC
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPUCLK_F
51 CPUCLK1
50 VDDLCPU
49 CPUCLK2
48 GND
47 CPU_STOP#
46 SDRAM_F
45 VDDSDR
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDSDR
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDD48
30 24MHz/FS0*
29 48MHz/FS1*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
PLL2
X1 XTAL
X2 OSC
÷2
STOP
FS[3:0]
MODE
CPU_STOP#
PCI_STOP#
{I 2 C
SCLK
SDATA
BUFFERIN
PLL1
Spread
Spectrum
LATCH
POR
4
Control
Logic
Config.
Reg.
STOP
PCI
CLOCK
DIVDER
STOP
STOP
48MHz
24MHz
IOAPIC_F
IOAPIC0
REF [1:0]
2
CPUCLK_F
1
CPUCLK [2:1]
2
6 PCICLK [5:0]
PCICLK_F
16 SDRAM [15:0]
SDRAM_F
Functionality
FS3 FS2 FS1 FS0
1111
1 1 10
110 1
1 10 0
10 11
10
10
100 1
10 0 0
0 111
0 110
0 10 1
0 100
00 11
00 10
000 1
0000
CPU
(MHz)
133
124
150
140
105
110
115
120
100.3
133
112
103
66.8
83.3
75
124
PCICLK (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.33 (CPU/2)
33.40 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
41.33 (CPU/2)
9250-08 Rev H 10/8/99
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Free Datasheet http://www.datasheet4u.com/

1 Page





9250-08 pdf, ピン配列
General Description
The ICS9250-08 is the single chip clock solution for Desktop/
designs using BX, Appollo Pro 133 type of chip sets. It provides
all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-08
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE
(Latched Input)
0
1
PCI_STOP#
(Input)
REF0
(Output)
ICS9250-08
Power Groups
VDDREF = REF [1:0], X1, X2
VDDPCI = PCICLK_F, PCICLK [5:0]
VDDSDR = SDRAM [15:0], supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLIOAPIC = IOAPIC_F
VDDLCPU = CPUCLK_F [2:1]
Third party brands and names are the property of their respective owners.
3
Free Datasheet http://www.datasheet4u.com/


3Pages


9250-08 電子部品, 半導体
ICS9250-08
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
46
49
51
52
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 SDRAM_F (Act/Inact)
1 CPUCLK2 (Act/Inact)
1 CPUCLK1 (Act/Inact)
1 CPUCLK_F (Act/Inact)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
8
16
14
13
12
11
9
PWD
DESCRIPTION
1 Reserved
1 PCICLK_F (Act/Inact)
1 PCICLK5 (Act/Inact)
1 PCICLK4 (Act/Inact)
1 PCICLK3 (Act/Inact)
1 PCICLK2 (Act/Inact)
1 PCICLK1 (Act/Inact)
1 PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
30
29
33, 32,
25, 24
22, 21,
19, 18
39, 38,
36, 35
44, 43,
41, 40
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 24MHz (Act/Inact)
1 48MHz (Act/Inact)
1 SDRAM(12:15) (Act/Inact)
1 SDRAM (8:11) (Act/Inact)
1 SDRAM (4:7) (Act/Inact)
1 SDRAM0 (0:3) (Act/Inact)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
X
1
1
X
1
1
X
1
DESCRIPTION
Latched FS0#
Reserved
Reserved
Latched FS1#
Reserved
Reserved
Latched FS3#
Reserved
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
54
55
-
-
2
3
PWD
DESCRIPTION
1 Reserved
X Latched FS2#
1 IOAPIC_F (Act/Inact)
1 IOAPIC0 (Act/Inact)
1 Reserved
1 Reserved
1 REF1 (Act/Inact)
1 REF0 (Act/Inact)
Third party brands and names are the property of their respective owners.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
6
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6 Page



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共有リンク

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部品番号部品説明メーカ
9250-08

ICS9250-08

Integrated Circuit Systems
Integrated Circuit Systems


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