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HIP7030A2P の電気的特性と機能

HIP7030A2PのメーカーはIntersil Corporationです、この部品の機能は「J1850 8-Bit 68HC05 Microcontroller」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP7030A2P
部品説明 J1850 8-Bit 68HC05 Microcontroller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP7030A2P Datasheet, HIP7030A2P PDF,ピン配置, 機能
HIP7030A2
ADVANCE INFORMATION
August 1996
J1850 8-Bit 68HC05 Microcontroller
Features
• Fully Supports VPW Specifications of SAE J1850
Standard for Class B Data Communications Network
Interface
• On-Chip Memory
• 176 Bytes of RAM
• 2110 Bytes of User ROM
• 13 Bidirectional I/O Lines
• 16-Bit Timer with Capture and Compare Registers
• Serial Peripheral Interface (SPI) System
• Watchdog Timer and Slow Clock Detect
• 10MHz Operating Frequency (5.0MHz Internal Bus
Frequency) at 5V
• Built-In-Test Bootstrap Mode with 242 Bytes of ROM
• Two Channel Analog Comparator
• On-Chip Oscillator Amplifier
• 8-Bit CPU Architecture
• Power-Saving STOP, WAIT and Data Retention Modes
• Full -40oC to 125oC Operating Range
• Single 3.0V to 6.0V Supply
• 28 Lead Dual-In-Line and Small Outline Plastic Pack-
ages
Software Features
• Standard 68HC05 Instruction Set
• True Bit Manipulation
• Addressing Modes Include Indexed Addressing
- Memory Mapped I/O
Ordering Information
PART NUMBER
HIP7030A2P
HIP7030A2M
TEMP.
RANGE (oC)
PACKAGE
-40 to 125 28 Lead Plastic
DIP
-40 to 125 28 Lead Plastic
SOIC (W)
PKG.
NO.
M28.3
E28.6
Description
The HIP7030A2 HCMOS Microcomputer is a member of the
CDP68HC05 family of low-cost single-chip microcomputers.
The integrated hardware functions provide the system
designer with a complete set of building blocks for
implementing a “Class B” multiplexed communications net-
work interface, which fully conforms to the VPW Multiplexed
Wiring protocol specified in SAE Recommended Practice
J1850. This 8-bit microcomputer unit (MCU) contains an on-
chip oscillator, CPU, 176 bytes of RAM, 2110 bytes of user
ROM, 13 I/O lines, a J1850 Variable Pulse Width Symbol
Encoder/Decoder (VPW SENDEC) system, a Serial Periph-
eral Interface (SPI) system, a two channel analog Compara-
tor, a Watchdog Timer, a Slow Clock Detect, and a 16-bit
Timer. The static HCMOS design allows operation at input
frequencies up to 10MHz (5MHz internal clock).
Table of Contents
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Electrical & Timing Specifications . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Integrated Hardware I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Built-In Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Programmable Timer
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . 27
J1850 VPW Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Symbol Encoder Decoder
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
COP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Effects of STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . 41
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outline Dimensions . . . . . . . . . . . . . . . . . . . . 55 - 56
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O, Control, Status and Data Register Definitions . . . . . . . 52
Ordering
Information Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3646.2

1 Page





HIP7030A2P pdf, ピン配列
HIP7030A2
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Input or Output Voltage
Pins with VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . . -0.3V to +10V
Current Drain Per Pin, I (Excluding VDD and VSS) . . . . . . . . 25mA
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . +265oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9000 Gates
Thermal Resistance (Typical)
θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60oC/W
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W
Maximum Package Power Dissipation at +125oC
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415mW
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325mW
Operating Temperature Range (TA) .
Storage Temperature Range (TSTG).
Junction Temperature . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.-40oC
.-65oC
......
to
to
..
+125oC
+150oC
+150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8•VDD) to VDD
Input Rise and Fall Time
CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max.
CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited
DC Electrical Specifications VDD = 5VDC ±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
No Load Output Voltage
Output High Voltage: PA0-7, PD0-4, VPWOUT,
TCMP
VOL
VOH
VOH
ILOAD < ±10µA
ILOAD = -0.8mA
-
VDD -0.1
VDD -0.8
-
-
VDD -0.4
0.1
-
-
Output High Voltage: OSCOUT
Output High Voltage: MISO, MOSI, SCK, OSCB
Output Low Voltage: OSCOUT
Output Low Voltage: MISO, MOSI, SCK, OSCB
Input High Voltage: PA0-7, PD0-4, MISO, MOSI,
SS, SCK
VOH
VOH
VOL
VOL
VIH
ILOAD = -0.08mA
ILOAD = -1.6mA
ILOAD = 0.17mA
ILOAD = 1.6mA
VDD -0.8
VDD -0.8
-
-
0.7•VDD
VDD -0.4
VDD -0.4
0.2
0.2
-
-
-
0.4
0.4
VDD
Input High Voltage: RESET, IRQ, TCAP,
VPWIN, OSCIN
VIH
0.8•VDD
-
VDD
Input Low Voltage: PA0-7, PD0-4, MISO, MOSI,
SS, SCK
VIL
VSS
- 0.3•VDD
Input Low Voltage: RESET, IRQ, TCAP, VPWIN,
OSCIN
VIL
VSS
- 0.2•VDD
Input Hysteresis Voltage: RESET, IRQ, TCAP,
VPWIN, OSCIN
VHYS
0.1•VDD 1.0 0.5•VDD
Supply Current
RUN
WAIT (Note 2)
STOP (Notes 2, 3)
I/O Ports Hi-Z Leakage Current: PA0-7, PD0-4,
MISO, MOSI, SCK
IRUN
IWAIT
ISTOP
IIL
fOSC = 10MHz Exter-
nal Square Wave
TA = 25oC
TA = -40oC to 125oC
-
-
-
-
-10
8
3.2
2
10
±0.01
18
10
50
250
+10
Input Current: RESET, IRQ, TCAP,
OSCIN, VPWIN, SS
IIN
-1 .001 +1
UNITS
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
3


3Pages


HIP7030A2P 電子部品, 半導体
Control Timing Diagrams
HIP7030A2
OSC1
(NOTE 1)
RESET
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
tRL
tILIH
tILCH
4064 tCYC
NOTE:
1. Represents the internal gating of the OSC1 pin.
FIGURE 1. STOP RECOVERY TIMING DIAGRAM
1FFE
RESET OR INTERRUPT
VECTOR FETCH
tTLTL
EXTERNAL
(TCAP PIN 1)
FIGURE 2.
Serial Peripheral Interface (SPI) Timing Diagrams
SS (INPUT)
HELD HIGH ON MASTER
(1)
(13)
SCK (OUTPUT)
MISO (INPUT)
MOSI (OUTPUT)
(4) (5)
D7I D6I
(6) (7)
D7O
(10) (11)
D6O
tTL
tTH
(12)
D0I
D0O
FIGURE 3A. SPI MASTER TIMING CPOL = 0, CPHA = 1
6

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共有リンク

Link :


部品番号部品説明メーカ
HIP7030A2

J1850 8-Bit 68HC05 Microcontroller

Intersil Corporation
Intersil Corporation
HIP7030A2M

J1850 8-Bit 68HC05 Microcontroller

Intersil Corporation
Intersil Corporation
HIP7030A2P

J1850 8-Bit 68HC05 Microcontroller

Intersil Corporation
Intersil Corporation


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