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HIP7010B の電気的特性と機能

HIP7010BのメーカーはIntersil Corporationです、この部品の機能は「J1850 Byte Level Interface Circuit」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP7010B
部品説明 J1850 Byte Level Interface Circuit
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP7010B Datasheet, HIP7010B PDF,ピン配置, 機能
HIP7010
ADVANCE INFORMATION
August 1996
J1850 Byte Level Interface Circuit
Features
• Fully Supports VPW (Variable Pulse Width) Messaging
Practices of SAE J1850 Standard for Class B Data
Communications Network Interface
- 3-Wire, High-Speed, Synchronous, Serial Interface
• Reduces Wiring Overhead
• Directly Interfaces with 68HC05 and 68HC11 Style SPI
Ports
• 1MHz, 8-Bit Transfers Between Host and HIP7010
Minimize Host Service Requirements
• Automatically Transmits Properly Framed Messages
• Prepends SOF to First Byte and Appends CRC to Last
Byte
• Fail-Safe Design Including, Slow Clock Detection
Circuitry, Prevents J1850 Bus Lockup Due to System
Errors or Loss of Input Clock
• Automatic Collision Detection
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol
(Noise/Illegal Symbols) Detection
• Supports In-Frame Responses with Generation of
Normalization Bits (NB) for Type 1, Type 2, and Type 3
Messages
• Wait-For-Idle Mode Reduces Host Overhead During
Non-Applicable Messages
• Status Register Flags Provide Information on Current
Status of J1850 Bus
• Serial I/O Pins are Active Only During Transfers - Bus
Available for Other Devices 95% of the Time
• TEST Pin Provides Built-in-Test Capabilities for
In-System Diagnostics and Factory Testing
• High Speed (4X) Receive Mode for Production and
Diagnostic Testing/Programming
• Operates with Wide Range of Input Clock Frequencies
• Power-Saving Power-Down Mode
• Full -40oC to +125oC Operating Range
• Single 3.0V to 6.0V Supply
Description
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a
member of the Intersil family of low-cost multiplexed wiring
ICs. The integrated functions of the HIP7010 provide the
system designer with components key to building a “Class B”
multiplexed communications network interface, which fully
conforms to the VPW Multiplexed Wiring protocol specified
in the SAE J1850 Standard. The HIP7010 is designed to
interface with a wide variety of Host microcontrollers via a
standard three wire, high-speed (1MHz), synchronous, serial
interface. The HIP7010 automatically produces properly
framed VPW messages, prepending the Start of Frame
(SOF) symbol and calculating and appending the CRC
check byte. All circuitry needed to decode incoming mes-
sages, to validate CRC bytes, and to detect Breaks, End of
Data (EOD), Idle bus, and illegal symbols is included. In-
Frame Responses (IFRs) are fully supported for Type 1,
Type 2, and Type 3 messages, with the appropriate Normal-
ization Bit automatically generated. The HCMOS design
allows proper opeSration at various input frequencies from
2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-
sil HIP7020.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG. NO.
HIP7010P
-40 +125 14 Lead Plastic DIP
E14.3
HIP7010B
-40 +125 14 Lead Plastic SOIC (N) M14.15
Pinout
HIP7010 (SOIC, PDIP)
TOP VIEW
IDLE 1
VPWIN 2
VPWOUT 3
VDD 4
RESET 5
TEST 6
SACTIVE 7
14 RDY
13 STAT
12 CLK
11 VSS
10 SIN
9 SOUT
8 SCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3644.2

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HIP7010B pdf, ピン配列
HIP7010
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V
Input or Output Voltage
Pins with VDD Diode . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V
Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to +10.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates
Thermal Resistance
θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100oC/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120oC/W
Maximum Package Power Dissipation at +125oC
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW
Operating Temperature Range (TA) .
Storage Temperature Range (TSTG).
Junction Temperature . . . . . . . . . . . .
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- 40oC
- 65oC
......
to
to
..
+125oC
+150oC
+150oC
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -40oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8VDD) to VDD
Input Rise and Fall Time
CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max
CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited
Electrical Specifications TA = -40oC to +125oC, VDD = 5VDC ±10%, Unless Otherwise Specified
PARAMETERS
SYMBOL CONDITIONS
MIN TYP
Supply Current
Operating Current
Power-Down Mode (Note 1)
Clock Stopped (Note 2)
Input High Voltage
IOP
IPD
ISTOP
CLK = 2.0 MHz
PD = 1
CLK = VSS or VDD
-
-
-
1.0
50
5.0
CMOS Level (SIN, STAT, RDY, TEST)
Schmitt Trigger (RESET, CLK, VPWIN)
Input Low Voltage
VIH
0.7VDD
0.8VDD
-
-
CMOS Level (SIN, STAT, RDY, TEST)
Schmitt Trigger (RESET, CLK, VPWIN)
High Level Input Current
VIL
VSS
VSS
-
-
(CLK, VPWIN, RESET)
IIH VIN = VDD
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-1 0.001
100 200
Low Level Input Current
(CLK, VPWIN, RESET)
IIL VIN = VSS
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-1 -0.001
-10 -0.01
Output High Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
Output Low Voltage
VOH
ILOAD = 0.8 mA
VDD-0.8
-
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
High Impedance Leakage Current
VOL ILOAD = -1.6 mA
-
-
Three-State with Pull-Down (SCK, SOUT)
Schmitt Trigger Hysteresis Voltage
(RESET, CLK, VPWIN)
IOZ
VHYS
VOUT = VDD
VOUT = VSS
100 200
-10
0.2 0.5
NOTES:
1. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; CLK = 10MHz.
2. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; PD = 1.
MAX
5.0
150
50
VDD
VDD
0.3VDD
0.2VDD
1
500
1
10
-
0.4
500
10
2.0
UNITS
mA
µA
µA
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
V
3


3Pages


HIP7010B 電子部品, 半導体
HIP7010
For enhanced noise immunity, the CLK input is a CMOS Schmitt
trigger input. See Electrical Specifications for input levels.
VPWOUT (Variable Pulse Width Out - Output),
VPWIN (Variable Pulse Width In - Input)
These two lines are used to interface to a J1850 bus trans-
ceiver, such as the Intersil HIP7020. VPWOUT is the vari-
able pulse width modulated output of the HIP7010’s symbol
encoder circuit. VPWIN is the inverted input to the symbol
decoder of the HIP7010. VPWIN is a Schmitt input.
SIN (Serial In - Input),
SOUT (Serial Out - Output),
SCK (Serial Clock - Output),
SACTIVE (Serial Bus Active - Output)
These four lines constitute the synchronous Serial Interface
(SERIAL) interface of the HIP7010. See the Serial Interface
(SERIAL) System for details. SIN, SOUT, and SCK provide
the three principal connections to the Host controller. SIN is a
CMOS input. SOUT and SCK are three-state outputs which
are only activated during serial transfers. The SIN, SOUT, and
SCK pins contain integrated pull-down load devices which
provide termination on the bus whenever it is in a high imped-
ance state. The SACTIVE pin is a CMOS output, which pulls
low when the HIP7010 is communicating on the serial bus.
See Serial Interface (SERIAL) System and Applications
Information for more details.
RDY (Byte Ready - Input)
The Byte Ready (RDY) line is a “handshaking” input from the
Host. Each rising edge on the RDY pin signifies that the Host
has loaded a byte into its SERIAL transmit register and the
HIP7010 can retrieve it (by generating clocks on SCK) when
the HIP7010 is ready for the data. See Serial Interface
(SERIAL) System and Applications Information for more
details.
The RDY pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.
IDLE (Idle/Service Request - Output)
The IDLE output pin indicates that the J1850 Bus has been
in a passive state for at least 275µs and is now idle. If the
bus has been passive for a minimum of 239µs and another
node initiates a new message, IDLE will pulse low for 1µs.
In its role as a Service Request pin, a reset forces IDLE
high. Following the reset, IDLE remains high for 17 CLK
cycles and is then driven low. IDLE will remain low until 40
CLK cycles +1.5µs after completion of the first Status/Con-
trol byte transfer. The IDLE pin will then resume its normal
role, remaining high until a 275µs lull (or 239µs plus a pas-
sive to active transition) has been detected on the J1850
bus. This provides a handshake mechanism to ensure the
Host will reinitialize the HIP7010 each time the HIP7010 is
reset via POR, RESET, or Slow Clock Detect.
If IDLE is low when an echo failure causes the ERR bit to be
set in the Status byte, the IDLE pin will pulse high for 2µs
and then return low (see Status/Control Register).
If IDLE is low when the host sets the NXT bit in the control
byte, the IDLE pin will pulse high for 2µs and then return low
(see Status/Control Register).
In general a Status/Control byte transfer should be performed
each time IDLE goes low. See Effects of Resets and Power-
Down and Applications Information for more details.
The IDLE pin is an active low CMOS output. See Operation
of the HIP7010 for more details.
STAT (Request Status/Control - Input)
The Request Status/Control (STAT) input pin is used by the
Host microcontroller to initiate an exchange of the Host’s con-
trol byte and the HIP7010’s status byte. A low to high transi-
tion on the STAT input signals the HIP7010 that the Host has
placed a control word in it’s SERIAL output register and is
ready to exchange it with the HIP7010’s status word. The
HIP7010 controls the exchange by generating the 8 SCKs
required. See Serial Interface (SERIAL) System and Appli-
cations Information for more details.
The STAT pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.
RESET (Reset - Input)
The RESET input is a low level active input, which resets the
HIP7010. Resetting the HIP7010 forces SACTIVE high, dis-
ables the SOUT and SCK pins, forces the VPWOUT output
low, drives IDLE high, and returns the internal state machine
to its initial state. Following reset, the HIP7010 is inhibited
from transmitting or receiving J1850 messages until a Sta-
tus/Control Register transfer has been completed (see
Effects Of Resets And Power-Down for more details).
The HIP7010 is also reset during initial power-on, by an
internal power-on-reset (POR) circuit.
Loss of a clock on the CLK input will cause a reset as
described previously under CLK.
If not used, the RESET pin should be tied to VDD.
For enhanced noise immunity, the RESET input is a CMOS
Schmitt trigger input. See Electrical Specifications for
input levels.
TEST (Test Mode - Input)
The TEST input provides a convenient method to test the
HIP7010 at the component level. Raising the TEST pin to a
high level causes the HIP7010 to enter a special TEST mode.
In the TEST mode, a special portion of the state machine is
activated which provides access to the Built-in-Test and diag-
nostic capabilities of the HIP7010 (see Test Mode for more
details).
The TEST pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected. In many
applications the TEST pin will be left unconnected, to allow
access via a board level ATE tester.
6

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共有リンク

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部品番号部品説明メーカ
HIP7010

J1850 Byte Level Interface Circuit

Intersil Corporation
Intersil Corporation
HIP7010B

J1850 Byte Level Interface Circuit

Intersil Corporation
Intersil Corporation
HIP7010P

J1850 Byte Level Interface Circuit

Intersil Corporation
Intersil Corporation


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