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PDF HIP6602B Data sheet ( Hoja de datos )
| Número de pieza | HIP6602B | |
| Descripción | Dual Channel Synchronous Rectified Buck MOSFET Driver | |
| Fabricantes | Intersil Corporation | |
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Dual Channel Synchronous Rectified
Buck MOSFET Driver
The HIP6602B is a high frequency, two power channel MOSFET
driver specifically designed to drive four power N-Channel
MOSFETs in a synchronous rectified buck converter topology. This
device is available in either a 14-lead SOIC or a 16-lead QFN
package with a PAD to thermally enhance the package. These
drivers combined with a HIP63xx or ISL65xx series of Multi-Phase
Buck PWM controllers and MOSFETs form a complete core voltage
regulator solution for advanced microprocessors.
The HIP6602B drives both upper and lower gates over a range of
5V to 12V. This drive-voltage flexibility provides the advantage of
optimizing applications involving trade-offs between switching
losses and conduction losses.
The output drivers in the HIP6602B have the capacity to efficiently
switch power MOSFETs at high frequencies. Each driver is capable
of driving a 3000pF load with a 30ns propagation delay and 50ns
transition time. This device implements bootstrapping on the upper
gates with a single external capacitor and resistor required for each
power channel. This reduces implementation complexity and allows
the use of higher performance, cost effective, N-Channel
MOSFETs. Adaptive shoot-through protection is integrated to
prevent both MOSFETs from conducting simultaneously.
Ordering Information
PKG.
PART NUMBER TEMP. RANGE (°C) PACKAGE DWG. #
HIP6602BCB
0 to 85
14 Ld SOIC M14.15
HIP6602BCB-T 14 Ld SOIC Tape and Reel
HIP6602BCBZ
(See Note 1)
0 to 85
14 Ld SOIC M14.15
(Pb-Free)
HIP6602BCBZ-T 14 Ld SOIC (Pb-Free) Tape and Reel
(See Note 1)
HIP6602BCR
0 to 85
16 Ld 5x5 QFN L16.5x5
HIP6602BCR-T 16 Ld 5x5 QFN Tape and Reel
Pinouts
HIP6602BCB/HIP6602BCBZ (SOIC)
TOP VIEW
June 2004
HIP6602B
FN9076.4
Features
• Drives Four N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Devices
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 14-Lead SOIC Package
• Smaller 16-Lead QFN Thermally Enhanced Package
• 5V to 12V Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Undervoltage Protection
• Pb-Free Product Now Available (SO8)
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Core Voltage Supplies for Intel Pentium® III and AMD®
AthlonTM Microprocessors.
• High-Frequency, Low-Profile DC-DC Converters
• High-Current, Low-Voltage DC-DC Converters
Note 1. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which is compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
HIP6602BCR (16 LEAD QFN)
TOP VIEW
PWM1 1
PWM2 2
GND 3
LGATE1 4
PVCC 5
PGND 6
LGATE2 7
14 VCC
13 PHASE1
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
8 PHASE2
16 15 14 13
GND 1
LG1 2
PVCC 3
PGND 4
12 UG1
11 BOOT1
10 BOOT2
9 UG2
5678
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
1 page  
HIP6602B
Functional Pin Descriptions
PWM1 (Pin 1) and PWM2 (Pin 2), (Pins 15 and 16
QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
GND (Pin 3), (Pin 1 QFN)
Bias and reference ground. All signals are referenced to
this node.
LGATE1 (Pin 4) and LGATE2 (Pin 7), (Pins 2 and 6
QFN)
Lower gate drive outputs. Connect to gates of the low-side
power N-Channel MOSFETs.
PVCC (Pin 5), (Pin 3 QFN)
This pin supplies the upper and lower gate drivers bias.
Connect this pin from +12V down to +5V.
PGND (Pin 6), (Pin 4 QFN)
This pin is the power ground return for the lower gate
drivers.
PHASE2 (Pin 8) and PHASE1 (Pin 13), (Pins 7 and
13 QFN)
Connect these pins to the source of the upper MOSFETs
and the drain of the lower MOSFETs. The PHASE voltage is
monitored for adaptive shoot-through protection. These pins
also provide a return path for the upper gate drive.
UGATE2 (Pin 9) and UGATE1 (Pin 12), (Pins 9 and
12 QFN)
Upper gate drive outputs. Connect to gate of high-side
power N-Channel MOSFETs.
Timing Diagram.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11), (Pins 10 and
11 QFN)
Floating bootstrap supply pins for the upper gate drivers.
Connect a bootstrap capacitor between these pins and the
corresponding PHASE pin. The bootstrap capacitor provides
the charge to turn on the upper MOSFETs. A resistor in
series with boot capacitor is required in certain applications
to reduce ringing on the BOOT pin. See the Internal
Bootstrap Device section under DESCRIPTION for guidance
in choosing the appropriate resistor and capacitor value.
VCC (Pin 14), (Pin 14 QFN)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND. To prevent forward
biasing an internal diode, this pin should be more positive
then PVCC during converter start-up
Description
Operation
Designed for versatility and speed, the HIP6602B two channel,
dual MOSFET driver controls both high-side and low-side
N-Channel FETs from two externally provided PWM signals.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDLLGATE], the
lower gate begins to fall. Typical fall times [TFLGATE] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [TPDHUGATE] based
on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[TRUGATE] and the upper MOSFET turns on.
PWM
TPDHUGATE
TRUGATE
TPDLUGATE
TFUGATE
UGATE
LGATE
TPDLLGATE
TFLGATE
5
TPDHLGATE
TRLGATE
5 Page 
HIP6602B
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45o
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1 0.0040 0.0098 0.10 0.25
-
B 0.013 0.020 0.33 0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.3367 0.3444 8.55
8.75
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC 1.27 BSC -
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L 0.016 0.050 0.40 1.27
6
N 14
14 7
α 0o 8o 0o 8o -
Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HIP6602B.PDF ] | |
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