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HIP6502EVAL1 の電気的特性と機能

HIP6502EVAL1のメーカーはIntersil Corporationです、この部品の機能は「Multiple Linear Power Controller with ACPI Control Interface」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP6502EVAL1
部品説明 Multiple Linear Power Controller with ACPI Control Interface
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP6502EVAL1 Datasheet, HIP6502EVAL1 PDF,ピン配置, 機能
Data Sheet
HIP6502
December 1999 File Number 4775.1
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6502 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3VDUAL/3.3VSB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply a choice of either or both of the computer system’s
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5VDUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5VDUAL output is offered through the EN5VDL pin. In active
state, the 3.3VDUAL and 3.3VMEM linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
external to the controller on the 3.3VDUAL, internal on the
3.3VMEM. Active state regulation on the 2.5VMEM output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5VDUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5VDUAL output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3VDUAL/3.3VSB output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5VCLK output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6502CB
0 to 70 20 Ld SOIC
HIP6502EVAL1 Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM (Active/Sleep)
- 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature;
Sleep State Only
- 2.5VMEM and 3.3VMEM Output: ±2.0% Over
Temperature; Both Operational States (3.3VMEM in
sleep only)
- 2.5VCLK Output: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 MSEL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

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HIP6502EVAL1 pdf, ピン配列
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
3.3VMEM
3.3V Q2
3.3VDUAL/ 3.3VSB
3.3V
FAULT
MSEL
Q6
Q3
HIP6502
LINEAR
REGULATOR
LINEAR
CONTROLLER
LINEAR
CONTROLLER
LINEAR
REGULATOR
HIP6502
CONTROL
LOGIC
Q1
VMEM
2.5V
VCLK
2.5V
SHUTDOWN
SX
EN5VDL
2
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
VOUT1
3.3VMEM
Q6
COUT1
Q2
VOUT3
3.3VDUAL/3.3VSB
Q3
COUT3
FAULT
SLP_S3
SLP_S5
EN5VDL
MSEL
SHUTDOWN
FIGURE 2.
12V
VSEN1
3V3
5V
3V3DLSB
5VSB
DRV2
VSEN2
Q1
3V3DL
COUT2
FAULT
S3
S5
EN5VDL
MSEL
SS
CSS
HIP6502
VCLK
COUT4
5VDLSB
DLA
5VDL
GND
Q5
COUT5
Q4
Q5
5VDUAL
5V
VOUT2
2.5VMEM
VOUT4
2.5VCLK
Q4
VOUT5
5VDUAL
FIGURE 3.
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HIP6502EVAL1 電子部品, 半導体
HIP6502
Functional Pin Description
3V3 (Pin 7)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 2V5CLK pin, and is monitored for
power quality.
5VSB (Pin 2)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides the output current for the VSEN1 and VSEN2 pins,
as well as the base current for Q2. The voltage at this pin is
monitored for power-on reset (POR) purposes.
5V (Pin 18)
Connect this pin to the ATX 5V output. This pin provides the
base bias current for Q1, and is monitored for power quality.
12V (Pin 17)
Connect this pin to the ATX 12V output. This pin provides the
gate bias voltage for Q3, Q5 and Q6, and is monitored for
power quality.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
S3 and S5 (Pins 9 and 10)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50k(typical) resistor pull-ups to
5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks any illegal state transitions (such as S3 to
S4/S5 or vice versa). Respectively, connect S3 and S5 to the
computer system’s SLP_S3 and SLP_S5 signals.
MSEL (Pin 20)
Unconnected, this pin is held at approximately 1.9V by an
internal resistor divider. Pulling this pin below 0.9V enables
the 2.5VMEM output and disables 3.3VMEM output. Pulling it
above 2.9V enables the 3.3VMEM output (typical voltage
levels) and disables 2.5V output. Leaving the pin open
enables both memory regulators.
EN5VDL (Pin 8)
This pin enables or disables sleep state support on the
5VDUAL output in response to S3 and S4/S5 requests. This
is a digital input pin whose status can only be changed
during active state operation or during chip shutdown (SS
pin grounded by external open-drain device or chip bias
below POR level). The input information is latched-in when
entering a sleep state, as well as following 5VSB POR
release or exit from shutdown. EN5VDL is internally pulled
high through a 40µA current source.
FAULT (Pin 12)
In case of an undervoltage on any of the outputs or on any of
the monitored ATX outputs, or in case of an overtemperature
event, this pin is used to report the fault condition by being
pulled to 5VSB.
SS (Pin 16)
Connect this pin to a small ceramic capacitor (no less than
5nF; 0.1µF recommended). The internal soft-start (SS)
current source along with the external capacitor creates a
voltage ramp used to control the ramp-up of the output
voltages. Pulling this pin low with an open-drain device shuts
down all the outputs as well as forces the FAULT pin low. The
CSS capacitor is also used to provide a controlled voltage
slew rate during active-to-sleep transitions on the 3.3VDUAL,
and VMEM outputs.
VSEN2 (Pin 1)
Connect this pin to the 2.5V memory output (VOUT2). In
sleep states, this pin is regulated to 2.5V through an internal
pass transistor capable of delivering 300mA (typically). The
active-state voltage at this pin is regulated through an
external NPN transistor connected at the DRV2 pin. During
all operating states, the voltage at this pin is monitored for
under-voltage events.
DRV2 (Pin 19)
Connect this pin to the base of a suitable NPN transistor.
This pass transistor regulates the 2.5V output from the ATX
3.3V during active states operation.
3V3DL (Pin 5)
Connect this pin to the 3.3V dual/stand-by output (VOUT3).
In sleep states, the voltage at this pin is regulated to 3.3V; in
active states, ATX 3.3V output is delivered to this node
through a fully on N-MOS transistor. During all operating
states, this pin is monitored for under-voltage events.
3V3DLSB (Pin 4)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 13)
Connect this pin to the gates of suitable N-MOSFETs, which
in active state, switch in the ATX 3.3V and 5V outputs into
the 3.3VMEM, 3.3VDUAL/3.3VSB and 5VDUAL outputs,
respectively.
5VDL (Pin 15)
Connect this pin to the 5VDUAL output (VOUT5). In either
operating state, the voltage at this pin is provided through a
fully on MOS transistor. This pin is also monitored for under-
voltage events.
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部品番号部品説明メーカ
HIP6502EVAL1

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation


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