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PDF HIP6502 Data sheet ( Hoja de datos )
| Número de pieza | HIP6502 | |
| Descripción | Multiple Linear Power Controller with ACPI Control Interface | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HIP6502
December 1999 File Number 4775.1
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6502 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3VDUAL/3.3VSB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply a choice of either or both of the computer system’s
2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5VDUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
5VDUAL output is offered through the EN5VDL pin. In active
state, the 3.3VDUAL and 3.3VMEM linear regulators use
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
external to the controller on the 3.3VDUAL, internal on the
3.3VMEM. Active state regulation on the 2.5VMEM output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5VDUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5VDUAL output is dictated not only by the status of the
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3VDUAL/3.3VSB output is active for as long as the ATX
5VSB voltage is applied to the chip. The 2.5VCLK output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP6502CB
0 to 70 20 Ld SOIC
HIP6502EVAL1 Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse (Active/Sleep)
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)
- 2.5VMEM RDRAM (Active/Sleep)
- 3.3VMEM SDRAM (Active/Sleep)
- 2.5VCLK Clock/Processor Terminations (Active Only)
• Excellent Output Voltage Regulation
- 3.3VDUAL/3.3VSB Output: ±2.0% Over Temperature;
Sleep State Only
- 2.5VMEM and 3.3VMEM Output: ±2.0% Over
Temperature; Both Operational States (3.3VMEM in
sleep only)
- 2.5VCLK Output: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6502
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
VSEN1 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 MSEL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
HIP6502
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
3V3DL Undervoltage Rising Threshold
- 2.77 -
V
3V3DL Undervoltage Hysteresis
- 110 -
mV
3V3DLSB Output Drive Current
DLA Output Impedance
I3V3DLSB 5VSB = 5V
5 8.5 -
- 90 -
mA
Ω
2.5VCLK LINEAR REGULATOR (VOUT4)
Regulation
- - 2.0 %
VCLK Nominal Voltage Level
VCLK Undervoltage Rising Threshold
VVCLK
- 2.5 -
- 2.10 -
V
V
VCLK Undervoltage Hysteresis
- 80 -
mV
VCLK Output Current (Note 2)
5VDUAL SWITCH CONTROLLER (VOUT5)
5VDL Undervoltage Rising Threshold
IVCLK V3V3 = 3.3V
500 800
-
- 4.22 -
mA
V
5VDL Undervoltage Hysteresis
- 170 -
mV
5VDLSB Output Drive Current
5VDLSB Pull-Up Impedance to 5VSB
I5VDLSB 5VDLSB = 4V, 5VSB = 5V
-20 - -40
- 350 -
mA
Ω
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 3)
20 25 30
ms
Active-to-Sleep Control Input Delay
- 200 -
µs
CONTROL I/O (S3, S5, EN5VDL, MSEL, FAULT)
High Level Input Threshold
- - 2.2 V
Low Level Input Threshold
0.8 -
-
V
S3, S5 Internal Pull-up Impedance to 5VSB
- 70 -
kΩ
FAULT Output Impedance
FAULT = high
- 100 -
Ω
TEMPERATURE MONITOR
Fault-Level Threshold (Note 4)
Shutdown-Level Threshold (Note 4)
140 -
- 155
-
-
oC
oC
NOTES:
2. At Ambient Temperatures Less Than 50oC.
3. Guaranteed by Correlation.
4. Guaranteed by Design.
5
5 Page 
HIP6502
+12VIN
+5VSB
CHF1
CSS
CBULK1
VOUT1
C12V
12V
SS
C5VSB
5VSB
5VDLSB
5VDL
CIN
VOUT5
Q4
VSEN1
CBULK5
CHF5
Q2
CHF3
VOUT3
CBULK3
3V3DLSB
HIP6502
3V3DL
DLA
5V
Q3
CBULK4
VCLK
VSEN2
Q6 3V3 GND DRV2
Q5
+5VIN
VOUT2 CHF2
Q1 CBULK2
CHF4
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 9. PRINTED CIRCUIT BOARD ISLANDS
A multi-layer printed circuit board is recommended. Figure 9
shows the connections of most of the components in the
converter. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s
components may require high quality capacitors to supply
the high slew rate (di/dt) current demands. Thus, it is
recommended that the output capacitors be selected for
transient load regulation, paying attention to their parasitic
components (ESR, ESL).
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the
power pass elements are conducting - during this time the
output capacitors have to supply all the output current. The
output voltage drop during this brief period of time can be
easily approximated with the following formula:
∆V O U T
=
IOUT
×
E
S
RO
U
T
+
C-----O--t--t-U----T-
, where
∆VOUT - output voltage drop
ESROUT - output capacitor bank ESR
IOUT - output current during transition
COUT - output capacitor bank capacitance
tt - active-to-sleep or sleep-to-active transition time (10µs typ.)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
VCLK (VOUT4) Output Capacitors Selection
The output capacitor for the VCLK linear regulator provides
loop stability. Figure 10 outlines a capacitance vs. equivalent
series resistance envelope. For stable operation and
optimized performance, select a COUT4 capacitor or
combination of capacitors with characteristics within the
shown envelope.
10
1
0.1
0.01
10
100
CAPACITANCE (µF)
FIGURE 10. COUT4 OUTPUT CAPACITOR
1000
Input Capacitors Selection
The input capacitors for an HIP6502 application have to
have a sufficiently low ESR as to not allow the input voltage
to dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the HIP6502’s regulation levels could have as a
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HIP6502.PDF ] | |
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