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PDF HIP6500B Data sheet ( Hoja de datos )
| Número de pieza | HIP6500B | |
| Descripción | Multiple Linear Power Controller with ACPI Control Interface | |
| Fabricantes | Intersil Corporation | |
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TM
Data Sheet
HIP6500B
May 2000
File Number 4870
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6500B complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output,
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output for operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power. A third controller powers up the 5VDUAL plane by
switching in the ATX 5V output in active states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Further control of the logic governing
activation of different power states is offered through two
configuration pins, EN3VDL and EN5VDL. In active state, the
3.3VDUAL linear regulator uses an external N-Channel pass
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses. In sleep state, power delivery on the 3.3VDUAL output is
transferred to an NPN transistor, also external to the controller.
Active state power delivery for the 2.5/3.3VMEM output is
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internal pass transistor. The 5VDUAL
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3VDUAL output, the operation of the
5VDUAL output is dictated not only by the status of the S3 and
S5 pins, but that of the EN5VDL pin as well. The 3.3VSB
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5VCLK output is only active during S0 and S1,
and uses the 3V3 pin as input source for its internal pass
element.
Ordering Information
PART NUMBER
HIP6500BCB
HIP6500BEVAL1
TEMP.
RANGE (oC)
PACKAGE
0 to 70 20 Ld SOIC
Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5V Active/Sleep (5VDUAL)
- 3.3V Active/Sleep (3.3VDUAL)
- 2.5V/3.3V Active/Sleep (2.5/3.3VMEM)
- 3.3V Always Present (3.3VSB)
- 2.5V Clock (Active Only) (2.5VCLK)
• Excellent Output Voltage Regulation
- 3.3VDUAL Output: ±2% Over Temperature; Sleep State
Only
- 2.5V/3.3VMEM Output: ±2% Over Temperature; Both
Operational States (3.3V setting in sleep only)
- 2.5VCLK and 3.3VSB Output: ±2% Over Temperature
• Small Size
- Very Low External Component Count
• Selectable Memory Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6500B
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
3V3SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 EN3VDL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HIP6500B
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
DRV2 Output Drive Current
DRV2 Output Impedance
3.3VDUAL LINEAR REGULATOR (VOUT3)
Sleep State Regulation
IDRV2
5VSB = 5V, RSEL = 1kΩ
RSEL = 10kΩ
220 -
- mA
- 200 -
Ω
- - 2.0 %
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
V3V3DL
- 3.3 -
- 2.739 -
V
V
3V3DL Undervoltage Hysteresis
- 99 - mV
3V3DLSB Output Drive Current
DLA Output Impedance
I3V3DLSB 5VSB = 5V
5 10 - mA
- 90 - Ω
2.5VCLK LINEAR REGULATOR (VOUT4)
Regulation
- - 2.0 %
VCLK Nominal Voltage Level
VCLK Undervoltage Rising Threshold
VVCLK
- 2.5 -
- 2.075 -
V
V
VCLK Undervoltage Hysteresis
- 75 - mV
VCLK Output Current (Note 4)
5VDUAL SWITCH CONTROLLER (VOUT5)
5VDL Undervoltage Rising Threshold
IVCLK
V3V3 = 3.3V
500 800
-
- 4.150 -
mA
V
5VDL Undervoltage Hysteresis
- 150 - mV
5VDLSB Output Drive Current
5VDLSB Pull-up Impedance to 5VSB
I5VDLSB 5VDLSB = 4V, 5VSB = 5V
-20 - -40 mA
- 350 -
Ω
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
20 25 30 ms
Active-to-Sleep Control Input Delay
- 200 -
µs
CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT/MSEL)
High Level Input Threshold
- - 2.2 V
Low Level Input Threshold
0.8 -
-V
S3, S5 Internal Pull-Up Impedance to 5VSB
- 50 - kΩ
FAULT Output Impedance
FAULT = high
- 100 -
Ω
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
Shutdown-Level Threshold (Note 6)
125 -
- 155
-
-
oC
oC
NOTES:
2. Sleep state only f9or 3.3V setting
3. Valid for 3.3V setting only.
4. At ambient temperatures less than 50oC.
5. Guaranteed by correlation.
6. Guaranteed by design.
5
5 Page 
HIP6500B
voltage is done by means of an external resistor connected
between the FAULT/MSEL pin and ground. An internal 40µA
(typical) current source creates a voltage drop across this
resistor. Following every 3.3VSB ramp-up or chip reset (see
Soft-Start Circuit), this voltage is compared with an internal
reference and the setting is latched in. Based on this
comparison, the output voltage is set at either 2.5V
(RSEL = 1kΩ), or 3.3V (RSEL = 10kΩ). It is very important
that no capacitor is connected to the FAULT/MSEL pin; the
presence of a capacitive element at this pin can lead to false
memory voltage selection. See Figure 11 for details.
Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slew-
up speed of the output voltages controlled by the HIP6500B,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
ΣICOUT = -C----S----S--I--S-×---S--V----B----G-- × (COUT × VOUT) , where
ISS - soft-start current (typically 10µA)
CSS - soft-start capacitor
VBG - bandgap voltage (typically 1.26V)
Σ(COUT x VOUT) - sum of the products between the
capacitance and the voltage of an output (total charge
delivered to all outputs).
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the HIP6500B
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the HIP6500B
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
Layout Considerations
The typical application employing a HIP6500B is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible, but not excessively far from the clock chip or
the processor. Insure the VSEN2 connection is properly
sized to carry 250mA without significant resistive losses;
similar guideline applies to the VCLK output, which can
deliver as much as 800mA (typical). As the current for the
VCLK output is provided from the ATX 3.3V, the connection
from the 3V3 pin to the 3.3V plane should be sized to carry
the maximum clock output current while exhibiting negligible
voltage losses. Similarly, the current for the 3.3VSB output is
provided from the 5VSB pin, and the output current on pin
DRV2 from the 5V pin - for best results, insure these pins are
connected to their respective sources through adequate
traces. The pass transistors should be placed on pads
capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
+12VIN
+5VSB
CHF1
CSS
CBULK1
VOUT1
C12V
12V
SS
C5VSB
5VSB
5VDLSB
5VDL
CIN
VOUT5
Q4
3V3SB
CBULK5
CHF5
Q2
CHF3
VOUT3
CBULK3
3V3DLSB
HIP6500B
3V3DL
DLA
5V
Q3
CBULK4
VCLK
VSEN2
3V3 GND DRV2
Q5
+5VIN
VOUT2 CHF2
Q1 CBULK2
CHF4
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HIP6500B.PDF ] | |
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