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HIP6500 の電気的特性と機能

HIP6500のメーカーはIntersil Corporationです、この部品の機能は「Multiple Linear Power Controller with ACPI Control Interface」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP6500
部品説明 Multiple Linear Power Controller with ACPI Control Interface
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP6500 Datasheet, HIP6500 PDF,ピン配置, 機能
Data Sheet
HIP6500
December 1999 File Number 4774.1
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6500 complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output,
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output for operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power. A third controller powers up the 5VDUAL plane by
switching in the ATX 5V output in active states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Further control of the logic governing
activation of different power states is offered through two
configuration pins, EN3VDL and EN5VDL. In active state, the
3.3VDUAL linear regulator uses an external N-Channel pass
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses. In sleep state, power delivery on the 3.3VDUAL output is
transferred to an NPN transistor, also external to the controller.
Active state power delivery for the 2.5/3.3VMEM output is
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internal pass transistor. The 5VDUAL
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3VDUAL output, the operation of the
5VDUAL output is dictated not only by the status of the S3 and
S5 pins, but that of the EN5VDL pin as well. The 3.3VSB
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5VCLK output is only active during S0 and
S1/S2, and uses the 3V3 pin as input source for its internal
pass element.
Ordering Information
PART NUMBER
HIP6500CB
HIP6500EVAL1
TEMP.
RANGE (oC)
PACKAGE
0 to 70 20 Ld SOIC
Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5V Active/Sleep (5VDUAL)
- 3.3V Active/Sleep (3.3VDUAL)
- 2.5V/3.3V Active/Sleep (2.5VMEM)
- 3.3V Always Present (3.3VSB)
- 2.5V Clock (Active Only) (2.5VCLK)
• Excellent Output Voltage Regulation
- 3.3VDUAL Output: ±2.0% Over Temperature; Sleep
State Only
- 2.5V/3.3VMEM Output: ±2.0% Over Temperature; Both
Operational States (3.3V setting in sleep only)
- 2.5VCLK and 3.3VSB Output: ±2.0% Over Temperature
• Small Size
- Very Low External Component Count
• Selectable Memory Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6500
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
3V3SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 EN3VDL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

1 Page





HIP6500 pdf, ピン配列
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
Q2
3.3VDUAL
3.3V
FAULT/MSEL
Q3
3.3VSB
3.3V
SHUTDOWN
SX
ENXVDL
2
2
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
HIP6500
LINEAR
REGULATOR
LINEAR
CONTROLLER
LINEAR
CONTROLLER
LINEAR
REGULATOR
HIP6500
CONTROL
LOGIC
FIGURE 2.
Q1
VMEM
2.5V/3.3V
VCLK
2.5V
Q4
Q5
5VDUAL
5V
VOUT1
3.3VSB
COUT1
Q2
VOUT3
3.3VDUAL
Q3
COUT3
FAULT
SLP_S3
SLP_S5
EN5VDL
EN3VDL
SHUTDOWN
12V
3V3SB
3V3
5V
3V3DLSB
5VSB
DRV2
Q1
VSEN2
3V3DL
FAULT/MSEL
RSEL
S3
S5
EN5VDL
EN3VDL
SS
CSS
HIP6500
GND
COUT2
VCLK
COUT4
5VDLSB
DLA
5VDL
Q5
COUT5
VOUT2
2.5/3.3VMEM
VOUT4
2.5VCLK
Q4
VOUT5
5VDUAL
FIGURE 3.
3


3Pages


HIP6500 電子部品, 半導体
HIP6500
Functional Pin Description
3V3 (Pin 7)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 2V5CLK pin, and is monitored for
power quality.
5VSB (Pin 2)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides the output current for the 3V3SB and VSEN2 pins,
as well as the base current for Q2. The voltage at this pin is
monitored for power-on reset (POR) purposes.
5V (Pin 18)
Connect this pin to the ATX 5V output. This pin provides the
base bias current for Q1, and is monitored for power quality.
12V (Pin 17)
Connect this pin to the ATX 12V output. This pin provides the
gate bias voltage for Q3 and Q5, and is monitored for power
quality.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
S3 and S5 (Pins 9 and 10)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50k(typical) resistor pull-ups to
5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks any illegal state transitions (such as S3 to
S4/S5 or vice versa). Respectively, connect S3 and S5 to the
computer system’s SLP_S3 and SLP_S5 signals.
EN3VDL and EN5VDL (Pins 20 and 8)
These pins control the logic governing the dual outputs’
behavior in response to S3 and S4/S5 requests. These are
digital inputs whose status can only be changed during
active states operation or during chip shutdown (SS pin
grounded by external open-drain device or chip bias below
POR level). The input information is latched-in when
entering a sleep state, as well as following 5VSB POR
release or exit from shutdown. EN3VDL features an internal
50kpull-down resistor, while EN5VDL is internally pulled
high through a similar resistor.
FAULT/MSEL (Pin 12)
This is a multiplexed function pin allowing the setting of the
memory output voltage to either 2.5V or 3.3V (for RDRAM or
SDRAM memory systems). In case of an undervoltage on
any of the outputs or on any of the monitored ATX outputs, or
in case of an overtemperature event, this pin is used to
report the fault condition by being pulled to 5VSB.
SS (Pin 16)
Connect this pin to a small ceramic capacitor (no less than 5nF;
0.1µF recommended). The internal soft-start (SS) current
source along with the external capacitor creates a voltage ramp
used to control the ramp-up of the output voltages. Pulling this
pin low with an open-drain device shuts down all the outputs as
well as forces the FAULT pin low. The CSS capacitor is also
used to provide a controlled voltage slew rate during active-to-
sleep transitions on the 3.3VDUAL, and VMEM outputs.
VSEN2 (Pin 1)
Connect this pin to the memory output (VOUT2). In sleep
states, this pin is regulated to 2.5V or 3.3V (based on RSEL)
through an internal pass transistor capable of delivering
300mA (typically). When VOUT2 is programmed to 2.5V, the
active-state voltage at this pin is regulated through an external
NPN transistor connected at the DRV2 pin. For the 3.3V
setting, the ATX 3.3V is passed to this pin through a fully on
external N-MOS transistor. During all operating states, the
voltage at this pin is monitored for under-voltage events.
DRV2 (Pin 19)
For the 2.5V RDRAM systems connect this pin to the base of
a suitable NPN transistor. This pass transistor regulates the
2.5V output from the ATX 3.3V during active states
operation. For 3.3V SDRAM systems connect this pin to the
gate of a suitable N-MOS transistor; this transistor is used to
switch in the ATX 3.3V output.
3V3DL (Pin 5)
Connect this pin to the 3.3V dual output (VOUT3). In sleep
states, the voltage at this pin is regulated to 3.3V; in active
states, ATX 3.3V output is delivered to this node through a
fully on N-MOS transistor. During all operating states, this
pin is monitored for under-voltage events.
3V3DLSB (Pin 4)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 13)
Connect this pin to the gates of suitable N-MOSFETs, which
in active state, switch in the ATX 3.3V and 5V outputs into
the 3.3VDUAL and 5VDUAL outputs, respectively.
5VDL (Pin 15)
Connect this pin to the 5VDUAL output (VOUT5). In either
operating state, the voltage at this pin is provided through a
fully on MOS transistor. This pin is also monitored for under-
voltage events.
5VDLSB (Pin 14)
Connect this pin to the gate of a suitable P-MOSFET or
bipolar PNP. In sleep state, this transistor is switched on,
connecting the ATX 5VSB output to the 5VDUAL regulator
output.
6

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部品番号部品説明メーカ
HIP6500

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation
HIP6500B

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation
HIP6500BCB

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation
HIP6500BEVAL1

Multiple Linear Power Controller with ACPI Control Interface

Intersil Corporation
Intersil Corporation


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