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PDF HIP6019 Data sheet ( Hoja de datos )
| Número de pieza | HIP6019 | |
| Descripción | ADJUSTABLE LDO AND 200mA ON-BOARD LDO | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HIP6019 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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Data Sheet No. PD94142
IRU3007
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRO-
NOUS, ADJUSTABLE LDO AND 200mA ON-BOARD LDO
FEATURES
Provides Single Chip Solution for Vcore, GTL+,
Clock Supply & 3.3V Switcher On-Board
Second switcher provides simple control for the
on-board 3.3V supply
200mA On-Board LDO Regulator
Designed to meet Intel VRM 8.2 and 8.3 specifica-
tion for Pentium II™
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear Regulator Controller On-Board for 1.5V
GTL+ supply
Loss-less Short Circuit Protection
Synchronous Operation allows maximum efficiency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum Part Count
Soft-Start
High current totem pole drivers for directly driving
the external Power MOSFETs
Power Good function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher outputs and generates a fault output
Thermal Shutdown
APPLICATIONS
Total Power Solution for Pentium II processor
application
DESCRIPTION
The IRU3007 controller IC is specifically designed to meet
Intel specification for Pentium II™ microprocessor ap-
plications as well as the next generation of P6 family
processors. The IRU3007 provides a single chip control-
ler IC for the Vcore, LDO controller for GTL+ and an
internal 200mA regulator for clock supply which are re-
quired for the Pentium II applications. It also contains a
switching controller to convert 5V to 3.3V regulator for
on-board applications that uses either AT type power
supply or is desired not to rely on the ATX power supply’s
3.3V output. These devices feature a patented topology
that in combination with a few external components, as
shown in the typical application circuit, will provide in
excess of 14A of output current for an on-board DC/DC
converter while automatically providing the right output
voltage via the 5-bit internal DAC. The IRU3007 also fea-
tures, loss-less current sensing for both switchers by
using the RDS(on) of the high-side power MOSFET as the
sensing resistor, internal current limiting for the clock
supply, a Power Good window comparator that switches
its open collector output low when any one of the out-
puts is outside of a pre-programmed window. Other fea-
tures of the device are: Under-Voltage Lockout for both
5V and 12V supplies, an external programmable soft-
start function, programming the oscillator frequency via
an external resistor, Over-Voltage Protection (OVP) cir-
cuitry for both switcher outputs and an internal thermal
shutdown.
TYPICAL APPLICATION
5V
Note: Pentium II and Pentium Pro are trademarks of Intel Corp.
VO U T 2
SWITCHER2
CONTROL
IRU3007
SWITCHER1
CONTROL
VO U T1
VO U T 3
LINEAR
CONTROL
LINEAR
REGULATOR
Figure 1 - Typical application of IRU3007.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
DEVICE
IRU3007CW
PACKAGE
28-pin Plastic SOIC WB (W)
Rev. 2.1
08/20/02
www.irf.com
VO U T4
1
1 page  
IRU3007
PIN#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN SYMBOL
Fb2
V5
SS
Fault / Rt
Fb4
VSEN2
VOUT4
Gnd
Gate3
Fb3
NC
Fb1
VSEN1
OCSet1
PGnd
LGate1
Phase1
UGate1
V12
PIN DESCRIPTION
This pin provides the feedback for the non-synchronous switching regulator. A resistor
divider is connected from this pin to VOUT2 and ground that sets the output voltage. The
value of the resistor connected from VOUT2 to Fb2 must be less than 100V.
5V supply voltage. A high frequency capacitor (0.1 to 1mF) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the soft-start for the 2 switching regulators. An internal resistor charges
an external capacitor that is connected from 5V supply to this pin which ramps up the
outputs of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the Soft-Start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if any of
the switcher outputs exceed the OVP trip point, the Fault pin switches to 12V and the
soft-start cap is discharged. If the Fault pin is to be connected to any external circuitry,
it needs to be buffered as shown in the application circuit.
This pin provides the feedback for the internal LDO regulator that its output is VOUT4.
This pin is connected to the output of the I/O switching regulator. It is an input that
provides sensing for the Under/Over-voltage circuitry for the I/O supply as well as the
power for the internal LDO regulator.
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Gate3.
No connection.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to VOUT1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from VOUT1 to Fb1 must be less than 100V.
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the CS threshold depending on the RDS of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1mF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high-side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1mF) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for noise free
operation.
Rev. 2.1
08/20/02
www.irf.com
5
5 Page 
IRU3007
APPLICATION INFORMATION
An example of how to calculate the components for the
application circuit is given below.
Assuming, two set of output conditions that this regula-
tor must meet for Vcore:
a) Vo=2.8V , Io=14.2A, DVo=185mV, DIo=14.2A
b) Vo=2V , Io=14.2A, DVo=140mV, DIo=14.2A
Also, the on-board 3.3V supply must be able to provide
10A load current and maintain less than ±5% total out-
put voltage variation.
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
Vcore
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total DVo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
ESR [ 100 = 7mV
14.2
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500mF, 6.3V has an ESR of less than 36mV typical.
Selecting 6 of these capacitors in parallel has an ESR
of ≈ 6mV which achieves our low ESR goal.
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
Gnd pin of the IRU3007 is 5mV and if the total DI, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level shift-
ing during the load transient eases the requirement for
the output capacitor ESR at the cost of load regulation.
One can show that the new ESR requirement eases up
by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without volt-
age level shifting must be 7mV then after level shifting
the new ESR will only need to be 8.5mV if the trace
resistance is 5mV (7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
Rs
[
2
3 (Vspec
-
0.02 3
DI
Vo
-
DVo)
Where :
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage spec
Vo = Output voltage
DVo = Output ripple voltage
DI = load current step
For example, assuming:
Vspec = ±140mV = ±0.1V for 2V output
Vo = 2V
DVo = assume 10mV = 0.01V
DI = 14.2A
Then the Rs is calculated to be:
3.3V supply
For the 3.3V supply, since there is not a fast transient
requirement, 2 of the 1500mF capacitors is sufficient.
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
Rs
≤
2
3 (0.140
-
0.02 3
14.2
2
-
0.01)
=
12.6mV
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6mV, the power dissipated is:
Io23Rs = 14.22312.6 = 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5mV, then the power dissipated is about 1W,
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7mV which translated to ≈ 6
Rev. 2.1
08/20/02
www.irf.com
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HIP6019.PDF ] | |
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