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PDF HIP6004E Data sheet ( Hoja de datos )
| Número de pieza | HIP6004E | |
| Descripción | Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor | |
| Fabricantes | Intersil Corporation | |
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TM
Data Sheet
HIP6004E
October 2001
File Number 4997.1
Buck and Synchronous-Rectifier (PWM)
Controller and Output Voltage Monitor
The HIP6004E provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004E integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004E includes a 5-input digital-
to-analog converter (DAC) that adjusts the output voltage
from 1.05VDC to 1.825VDC in 25mV increments steps. The
precision reference and voltage-mode regulator hold the
selected output voltage to within ±1% over temperature and
line voltage variations.
The HIP6004E provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The HIP6004E monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The HIP6004E
protects against over-current and overvoltage conditions by
inhibiting PWM operation. Additional built-in overvoltage
protection triggers an external SCR to crowbar the input
supply. The HIP6004E monitors the current by using the
rDS(ON) of the upper MOSFET which eliminates the need for
a current sensing resistor.
Pinout
HIP6004E
TOP VIEW
VSEN 1
OCSET 2
SS 3
VID25mV 4
VID0 5
VID1 6
VID2 7
VID3 8
COMP 9
FB 10
1
20 RT
19 OVP
18 VCC
17 LGATE
16 PGND
15 BOOT
14 UGATE
13 PHASE
12 PGOOD
11 GND
Features
• Drives two N-Channel MOSFETs
• Operates from +5V or +12V Input
• Simple single-loop control design
- Voltage-mode PWM control
• Fast transient response
- High-bandwidth error amplifier
- Full 0% to 100% Duty Ratio
• Excellent output voltage regulation
- ±1% Over Line Voltage and Temperature
• 5-Bit digital-to-analog output
Voltage Selection
- 25mV binary steps . . . . . . . . . . . 1.05VDC to 1.825VDC
• Power good output voltage monitor
• Overvoltage and overcurrent fault monitors
- Does not require extra current sensing element,
Uses MOSFET’s rDS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
Applications
• VRM8.5 modules for Pentium III and Other
Microprocessors
• High-Power DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART NUMBER
HIP6004ECB
HIP6004ECV
TEMP.
RANGE (oC)
PACKAGE
0 to 70 20 Ld SOIC
0 to 70 20 Ld TSSOP
PKG.
NO.
M20.3
M20.173
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the part in tape and reel, e.g., HIP6004ECB-T.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
Pentium® is a registered trademark of Intel Corporation.
1 page  
HIP6004E
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Fs ≈ 200kHz + R-5----T-x---(--k-1---Ω0---6--)
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
following equation:
Fs ≈ 200kHz – R-4----T-x---(--k-1---Ω0----7-)
(RT to 12V)
RT pin has a constant voltage of 1.26V typically.
Functional Description
Initialization
The HIP6004E automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (VIN) on the OCSET pin. The level on
OCSET is equal to VIN less a fixed voltage drop (see over-
current protection). The POR function initiates soft-start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, VIN
and VCC are equivalent and the +12V power source must
exceed the rising VCC threshold before POR initiates operation.
Soft Start
The POR function initiates the soft-start sequence. An internal
10µA current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft-start interval with
CSS = 0.1µF. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t1 in Figure 3,
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
of increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2. With sufficient
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t2 and t3 in Figure 3.
At t3 the SS voltage exceeds the DACOUT voltage and the
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±10% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
PGOOD
(2V/DIV.)
0V
SOFT-START
(1V/DIV.)
OUTPUT
VOLTAGE
(1V/DIV.)
0V
0V
t1 t2
t3
TIME (5ms/DIV.)
FIGURE 3. SOFT START INTERVAL
Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, rDS(ON)
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
4V
2V
0V
15A
10A
5A
0A
TIME (20ms/DIV.)
FIGURE 4. OVER-CURRENT OPERATION
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the overcurrent trip level. An internal 200µA current
5
5 Page 
HIP6004E
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
E1
-B-
E
0.25(0.010) M B M
GAUGE
PLANE
123
0.05(0.002) SEATING PLANE
-A-
D
A
0.25
0.010
L
-C-
e A1
b
0.10(0.004) M C A M B S
α
A2
0.10(0.004)
c
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A - 0.047 - 1.20 -
A1
0.002 0.006
0.05
0.15
-
A2
0.031 0.051
0.80
1.05
-
b
0.0075 0.0118 0.19
0.30
9
c
0.0035 0.0079 0.09
0.20
-
D
0.252 0.260
6.40
6.60
3
E1
0.169 0.177
4.30
4.50
4
e 0.026 BSC 0.65 BSC -
E
0.246 0.256
6.25
6.50
-
L
0.0177 0.0295 0.45
0.75
6
N 20
20 7
α
0o 8o 0o 8o
-
Rev. 1 6/98
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HIP6004E.PDF ] | |
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