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HIP5061DS の電気的特性と機能

HIP5061DSのメーカーはIntersil Corporationです、この部品の機能は「7A/ High Efficiency Current Mode Controlled PWM Regulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP5061DS
部品説明 7A/ High Efficiency Current Mode Controlled PWM Regulator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP5061DS Datasheet, HIP5061DS PDF,ピン配置, 機能
HIP5061
April 1994
Features
• Single Chip Current Mode Control IC
• 60V, On-Chip DMOS Power Transistor
• Thermal Protection
• Over-Current Protection
• 250kHz Operation
• Output Rise and Fall Times - 10ns
• On-Chip Reference Voltage - 5.1V
• Slope Compensation
• VDD Clamp Allows 10.8V to 60V Supply
• Supply Current Does Not Increase When Power
Device is On
Applications
• Distributed / Board Mounted Power Supplies
• DC - DC Converter Modules
• Voltage Inverters
• Small Uninterruptable Power Supplies
• Cascode Switching for Off Line SMPS
7A, High Efficiency Current
Mode Controlled PWM Regulator
Description
The HIP5061 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC. The
standard “Boost”, “Buck-Boost”, “Cuk”, “Forward”, “Flyback”
and the “SEPIC” (Single-Ended Primary Inductance Con-
verter) power supply topologies may be implemented with
this single control IC.
Over-temperature and rapid short-circuit recovery circuitry is
incorporated within the IC. These protection circuits disable
the drive to the power transistor to protect the transistor and
insure rapid restarting of the supply after the short circuit is
removed.
As a result of the power DMOS transistors current (7A at 30%
duty cycle, 5A DC) and 60V capability, supplies with output
power over 50W are possible.
Ordering Information
PART TEMPERATURE
NUMBER
RANGE
PACKAGE
HIP5061DS 0oC to +85oC 7 Lead Staggered “Gullwing” SIP
Pinout
HIP5061 (SIP)
TOP VIEW
Simplified Functional Diagram
VIN
SOURCE
(TAB)
PIN 7 VDD
PIN 6 VG
PIN 5 DRAIN
PIN 4 SOURCE
PIN 3 FB
PIN 2 VC
PIN 1 GND
DO NOT
USE
HIP5061
CLOCK
OVER
TEMP
VDD
VDD CLAMP
CONTROL
LOGIC
VG
GATE
DRIVER
V/I
DRAIN
SOURCE
(TAB)
AMP
VC
FB
UNDER
VOLTAGE
SLOPE
COMPENSATION
2.5V
5.1V
REFERENCE
GND
VOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207 | Copyright © Intersil Corporation 1999
7-53
File Number 3390.2

1 Page





HIP5061DS pdf, ピン配列
Specifications HIP5061
Electrical Specifications VDD = VG =12V, VC = 5V, VFB = 5.1V, SOURCE = GND = DRAIN = 0V, TJ = 0oC to +105oC,
Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
CURRENT CONTROLLED PWM
gm(VC)
V/IREF
IDRAIN, PEAK /VC
Voltage to Current Converter Ref-
erence Voltage
Note 3
IDRAIN = 0.25A, Note 3
tBT Current Comparator Blanking Note 3
Time
tONMIN
tOFFMIN
MinCI
Minimum DMOS “ON” Time
Minimum DMOS “OFF” Time
Minimum Controllable DMOS
Peak Current
Note 3
Note 3
Note 3
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 6% to 30%, Note 3
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 30% to 96%, Note 3
CURRENT COMPENSATION RAMP
I/t
tRD
Compensation Ramp Rate
Compensation Ramp Delay
IDRAIN, PEAK /Time, Note 3
Note 3
START-UP
VDDMIN
VDDHYS
VCEN
Rising VDD Threshold Voltage
Power-On Hysteresis
Enable Comparator Threshold
Voltage
VFB = 4V
VFB = 4V
RVC Power-Up Resistance
THERMAL MONITOR
4V < VDD < 10.8V, VC = 0.8V
TJ Substrate Temperature for
Thermal Monitor to Trip
Note 4
TJHY
Temperature Hysteresis
Note 4
NOTES:
1. All Voltages relative to pin 1, GND.
2. VD = 10V, Starting TJ = +25oC, L = 4mH, IPEAK = 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.
MIN
TYP
MAX
UNITS
1.4 2.2 3.0 A/V
2.4 2.8 3.1
V
40 100 175
ns
60 150 250
ns
40 125 200
ns
-
100 250
mA
7 9.5 12
A
5 8 12 A
-1.4
- 0.85
- 0.45
A/µs
1.3 1.5 1.8
µs
9.3 10.3 10.8
0.3 0.45 0.6
1.0 1.5 2.0
50 500 3000
105 - 145
-5-
V
V
V
oC
oC
TABLE 1. CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT
VD (V)
10
IL
(PEAK AMPS)
5
L (mH)
40
EAS (mJ)
550
10 7 4TZ 120
6 10 0.33 18
6 12.5 0.14 12
NOTE: Device Selected to Obtain Peak Current without Clocking
7
HIP5061
1
VARY tP TO OBTAIN
REQUIRED PEAK IL
12V
tP
L
+
IL -VD
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
7-55


3Pages


HIP5061DS 電子部品, 半導体
HIP5061
Pin Description
TERMINAL
NUMBER
DESIGNATION
DESCRIPTION
1
GND
This is the analog ground terminal of the IC.
2 VC The output of the transconductance amplifier appears at this terminal. Input to the internal
voltage to current converter also appears at this node. Transconductance amplifier gain
and loop response are set at this terminal. When the VDD terminal voltage is below the
starting voltage, VDDMIN, this terminal is held low. When the voltage at this terminal
exceeds VCMAX, 7V typical, implying an over-current condition, a typical 10mA current,
IVCOVER pulls this terminal towards ground. This current remains “ON” until the voltage on
the VC terminal falls by VCHYS, typically 1.1V, below the upper threshold, VCMAX. When the
voltage on this terminal falls below VCEN, typically 1.5V, the IC is disabled.
3 FB Feedback from the regulator output is applied to this terminal. This terminal is the input to
the transconductance amplifier. The amplifier compares the internal 5.1V reference and
the feedback signal from the regulator output.
4
SOURCE
The terminal, labeled TAB, has a connection to this terminal, but because of the long lead
length and resulting high inductance of this terminal, it should not be used as a means of
bypassing. Therefore, this terminal is labeled “Do Not Use.”
5
DRAIN
Connection to the Drain of the internal power DMOS transistor is made at this terminal.
6 VG Gate drive supply voltage is provided at this terminal. A 10to 150resistor connected
between this terminal and the VDD terminal provides decoupling and the supply voltage
for the gate drivers.
7 VDD External supply input to the IC. A nominal 14V shunt regulator is connected between this
terminal and the TAB. A series resistor should be connected to this terminal from the
external voltage source to supply a minimum current of 33mA and a maximum current of
105mA under the worst cast supply voltage. The series resistor is not required if the
supply voltage is 12V, ±10%.
TAB
SOURCE
This is the internal power DMOS transistor Source terminal. It should be used as the
ground return for the VDD bypass capacitor. In addition high frequency bypassing for both
the regulator output load voltage and supply input voltage should be returned to this
terminal.
For more information refer to Application Notes AN9208, AN9212, AN9323.
Foot Print For Soldering
0.120
0.523
OPTIONAL Ø 0.151
LIMIT OF SOLDER MASK
FOR HEADER
0.212
0.424
0.050 TYP
0.480
0.575
0.675
TO-220 STAGGERED GULL WING SIP
0.050 TYP
0.080 TYP
7-58

6 Page



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部品番号部品説明メーカ
HIP5061DS

7A/ High Efficiency Current Mode Controlled PWM Regulator

Intersil Corporation
Intersil Corporation


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