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PDF HIP5020 Data sheet ( Hoja de datos )
| Número de pieza | HIP5020 | |
| Descripción | Integrated-Power Buck Converter Controller with Synchronous Rectification | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HIP5020
January 1997
File Number 4243
Integrated-Power Buck Converter
Controller with Synchronous Rectification
The HIP5020 is a high-efficiency, buck converter controller
with synchronous rectification and integral power MOSFETs.
Integrated current sensing eliminates the external resistor
and saves power. The controller combines two methods of
regulation: Current mode control for outstanding regulation
response to large signal load transients, and Hysteretic
mode control for high efficiency at low output currents.
The HIP5020 controller offers a high degree of flexibility.
Small components set the switching frequency, the soft-start
interval and the load current boundary between Run and
Hysteretic modes. These adjustments enable the designer
to best optimize the trade-offs of cost, efficiency and size.
The example application guide section illustrates these
trade-offs with component and vendor suggestions for three
circuit designs. These designs are suitable for use without
modification. However, the block diagram, detailed
description and HIP5020 component specifications enable
further optimization to meet specific requirements.
Features
• High Efficiency - Above 95%
• Integrated N-Channel Synchronous Rectifier
and Upper MOSFETs - 75mΩ Each
• Wide Input Voltage and Load Range
- 4.5VDC to 18VDC (5 to 12 NiCd Battery Cells)
- Up to 3.5ADC
• Automatically Switches Regulation Mode
- Current Mode Control for Excellent Performance at
High Load Currents
- Hysteretic Control for High Efficiency at Light Load
Currents
• Flexible and Easy to Use
- Ready-to-Use Example Applications
- Custom Optimization with Small Components
- Design and Simulation Software Available
• Integrated, Low-Loss Current Sensing
• Over-Current Protection
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HIP5020DB
0 to 70 28 Ld SOIC
PKG.
NO.
M28.3
• Adaptive Dead-Time - Eliminates Shoot-Through
• 100kHz to 1MHz PWM Switching Frequency
• Thermally Enhanced SOIC Package
Applications
Pinout
HIP5020 (SOIC)
TOP VIEW
VIN 1
VIN 2
VIN 3
PHASE 4
PHASE 5
6
PGND 7
(WEB) 8
9
GND 10
FB 11
VINF 12
HMI 13
SLOPE 14
28 PHASE
27 PHASE
26 SD
25 SOFT
24 OVLD
23
22 PGND
21 (WEB)
20
19 CP-
18 CP+
17 VCC
16 BOOT
15 CT
• Notebook Computers
• Portable Telecommunications
• Portable Instruments
Typical Application
HIP5020
MODE
CONTROL AND
VIN PROTECTION
INTERNAL
SUPPLY
100
VIN = 6V
95 VO = 5V
90 VIN = 5V
VO = 3.3V
85
80
0.001 0.01 0.1 1 10
L1 LOAD CURRENT (A)
14µH
440µF
C1 VOUT
REGULATION
AND CONTROL
2-13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HIP5020
+
VIN
-
VIN VCC
R5 C2
C12
C5
CP+
BOOT
HIP5020
PHASE
CP-
C10 ON/OFF
VINF
SD
CT
PGND
FB
SLOPE
OVLD
C6
SOFT GND HMI
C7
C8 R4
D1 C4
C3
L1
R6
D2
C9 R1
R2
VO
C1
FIGURE 1. EXAMPLE APPLICATION CIRCUIT
TABLE 1. EXAMPLE APPLICATION PERFORMANCE PARAMETERS
These characteristics are for the circuit shown in Figure 1 with the components given in Tables 2 and 3.
PARAMETER
CONDITIONS
CIRCUIT 1
HIGH EFFICIENCY
CIRCUIT 2
SMALL SIZE
CIRCUIT 3
LOW COST
Input Voltage
- Typical
- Range
3 Li-Ion Cells:
11.1
8.1 to 16
2 Li-Ion Cells:
7.4
5.4 to 12
9 Nicd Cells:
10.8
8.1 to 16
Switching Frequency
200 ±15%
625 ±15%
120 ±20%
Output Voltage Variation
Line Regulation
Load Regulation
Output Voltage Ripple
- Full Load
- Light Load
Efficiency
- Full load
- Peak
- Light Load
Estimated Circuit Area
Tallest Component
Initial Setting
Input Voltage Range; IO = 1ADC
IO = 0.1 to 3ADC, VIN = Typical
Bandwidth < 20MHz
IO = 3ADC, VIN = Typical
IO = 50mADC, VIN = Typical
IO = 3ADC, VIN = Typical
0.5 < IO < 2ADC, VIN = Typical
IO = 50mADC, VIN = Typical
3.3 ±3.5%
±0.1
±0.3
18
50
86
92
88
3.5
0.45
3.3 ±2.2%
±0.1
±0.3
30
80
86
89
84
2.1
0.24
3.3 ±3.5%
±0.1
±0.4
20
70
86
90
72
3.6
0.68
Normalized Circuit Cost Ratio of total circuit cost to Circuit 2
1.1
1 0.75
UNITS
VDC
kHz
V
%
%
mV
%
%
%
in2
in
COMPONENT
D1
D2
L1
C1
C2
C3
TABLE 2. COMPONENT SUGGESTIONS FOR EXAMPLE APPLICATION CIRCUITS
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
MBR0540
MBR0540
1N4148
MBR0540
Not Used
Not Used
16µH, RDC < 15mΩ
2x - 220µF, 10V OS-CON
ESRMAX (100kHz) < 35mΩ
100µF, 20V OS-CON
ESRMAX (100kHz) < 30mΩ
0.1µF ±20% - Ceramic
5µH, RDC < 22mΩ
3x - 220µF, 10V Tantalum
ESRMAX (100kHz) < 100mΩ
2x - 100µF, 16V Tantalum
ESRMAX (100kHz) < 100mΩ
0.1µF ±10% - Ceramic
26µH, RDC < 25mΩ
3x - 390µF, 25V, Aluminum
ESRMAX (100kHz) < 65mΩ
2x - 390µF, 25V Aluminum
ESRMAX (100kHz) < 65mΩ
0.1µF ±20% - Ceramic
2-17
5 Page 
HIP5020
Using the built-in 12pF integration capacitor across the error
amplifier, the transfer function, G(s) for the lead-lag network is:
G(s) = K-s-- • 1-1----++-----ss-----⁄⁄--ωω-----pz-
where K = R-----1-----•----1----2--1---•----1---0----–---1---2-
ωz = (---R-----1-----+-----R--1--6----)----•----C-----9-
and ωp = R-----6-----1•----C-----9--
The HIP5020 design and simulation software (available at
the Harris WEB site) computes these values and greatly
simplifies the following compensation design process. To
design a DC-DC converter for stable operation:
1. Determine the output capacitor’s ESR zero frequency,
fESR which is given by: 1 ⁄ (2 • π • C1 • ESR)
2. Place the compensation pole (ωp/2π) at the ESR zero fre-
quency, fESR.
3. Determine the desired converter bandwidth (or the fre-
quency where the loop gain is unity). Bandwidth must be
below 1/2 the switching frequency. A reasonable band-
width is approximately 1/10 the switching frequency.
4. Select the compensation zero (ωz) well below the desired
bandwidth frequency and adjust as necessary to achieve
the desired phase margin (40o Minimum).
5. Adjust the gain (via R1) and iterate the compensation zero
and gain as needed to achieve the desired bandwidth
and phase margin.
6. Measure the closed-loop transfer function at both mini-
mum and maximum input voltage and at both full load
and the Run-to-Hysteretic mode load current boundary.
Be sure to note the phase margin and the gain margin.
The single component R1 can compensate the control loop if
the detailed characteristics of the output capacitor, bandwidth,
and switching frequency meet strict requirements. The
bandwidth (or unity gain frequency) must be much greater
than the ESR zero frequency (fESR) and much less than twice
the switching frequency. Additionally the break frequency of
output capacitor’s ESL must be much greater than the
switching frequency. If these conditions exist, the ESR zero
provides the necessary phase boost. However, note that the
ESR is not a well controlled parameter and is variable with
temperature and aging. Select R1 for the proper
compensation gain and confirm the selection with closed-loop
measurements. Additionally determine the worst case ESR
variation and estimate this effect on converter stability.
Output Voltage Setting
The resistor divider R1 and R2 sets the output voltage as a
function of the reference voltage. Select R1 to achieve the
desired bandwidth then determine R2 from:
R2
=
R
1
•
--------1---.--2---6---------
VO – 1.26
The output voltage regulation improves with the use of
integrated resistor network. By integrating the resistors, the
variations of R1 track the variations of R2. The ratio of R1 to
R2 remains constant and this minimizes the output voltage
variation to improve regulation. Integrated resistor networks
are available in small SOT-23 packages such as the one
used in Circuit 2.
Slope Compensation
Slope compensation is necessary to avoid current loop
instability for duty ratios above 50%. Select C7 to set the
amount of slope compensation according to the following:
C7MAX = L----1-----•----2----7V---2-O----•----1----0---–---6-
This value of capacitance provides a compensation ramp that is
1/2 of the reflected output inductor decreasing current slope.
Charge Pump and Bootstrap Design
The charge pump and bootstrap circuit supply the internal
bias power for the HIP5020. The majority of the bias power
goes to gate drives. The charge pump operates at the
switching frequency for input voltage below 9.8V. Select
capacitors C4 and C5 according to the following:
C4, C5MIN
=
-0---.--0---8---8--
FS
+
0.
12
•
10–6
The gate of the upper N-Channel MOSFET is driven above
the input voltage by the internal gate drive with power
supplied by the bootstrap circuit D1 and C3. A fast recovery,
low leakage diode is recommended for D1. C3 should be a
high quality ceramic capacitor.
Hysteretic Mode Current Setting
The voltage on the HMI pin sets the load current boundary
between Run mode and Hysteretic mode. This setting
enables the designer to trade-off efficiency and output
voltage ripple at low output current. The output voltage ripple
is higher in Hysteretic mode as compared with Run mode.
Many systems can tolerate higher power supply ripple at
light loads because the reduced load induced ripple. The
designer should select the load current boundary based
upon converter efficiency characteristics and known load
characteristics. For example, a HIP5020 converter powering
a microprocessor load might select the HMI boundary
between the sleep and active states of operation.
The ripple voltage is highest for load current just below the
mode boundary. The ripple voltage is a function of the
hysteresis width, the resistors R1 and R2, the hysteretic
current setting (HMI) and the output capacitor ESR as
described in the Hysteretic Mode section.
Figure 9 shows the efficiency versus load for two different
VHMI settings. The efficiency at light load current is higher
with a higher settings. The efficiency at light load current is
higher VHMI setting. However, the more efficient design has
2-23
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HIP5020.PDF ] | |
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