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PDF HIP4020 Data sheet ( Hoja de datos )
| Número de pieza | HIP4020 | |
| Descripción | Half Amp Full Bridge Power Driver for Small 3V/ 5V and 12V DC Motors | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HIP4020
June 1997
Half Amp Full Bridge Power Driver
for Small 3V, 5V and 12V DC Motors
Features
Description
• Two Independent Controlled Complementary
MOS Power Output Half H-Drivers (Full-Bridge)
for Nominal 3V to 12V Power Supply Operation
• Split ±Voltage Power Supply Option for Output
Drivers
• Load Switching Capabilities to 0.5A
• Single Supply Range +2.5V to +15V
• Low Standby Current
• CMOS/TTL Compatible Input Logic
• Over-Temperature Shutdown Protection
• Over-Current Limit Protection
• Over-Current Fault Flag Output
• Direction, Braking and PWM Control
Applications
• DC Motor Driver
• Relay and Solenoid Drivers
• Stepper Motor Controller
• Air Core Gauge Instrument Driver
• Speedometer Displays
• Tachometer Displays
• Remote Power Switch
• Battery Operated Switch Circuits
• Logic and Microcontroller Operated Switch
In the Functional Block Diagram of the HIP4020, the four switches
and a load are arranged in an H-Configuration so that the drive volt-
age from terminals OUTA and OUTB can be cross-switched to
change the direction of current flow in the load. This is commonly
known as 4-quadrant load control. As shown in the Block Diagram,
switches Q1 and Q4 are conducting or in an ON state when current
flows from VDD through Q1 to the load, and then through Q4 to termi-
nal VSSB; where load terminal OUTA is at a positive potential with
respect to OUTB. Switches Q1 and Q4 are operated synchronously
by the control logic. The control logic switches Q3 and Q2 to an open
or OFF state when Q1 and Q4 are switched ON. To reverse the cur-
rent flow in the load, the switch states are reversed where Q1 and Q4
are OFF while Q2 and Q3 are ON. Consequently, current then flows
from VDD through Q3, through the load, and through Q2 to terminal
VSSA, and load terminal OUTB is then at a positive potential with
respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A and B
Input Controls. The ILF output is an Over-Current Limit Fault Flag Out-
put and indicates a fault condition for either Output A or B or both. The
VDD and VSS are the Power Supply reference terminals for the A and
B Control Logic Inputs and ILF Output. While the VDD positive power
supply terminal is internally connected to each bridge driver, the VSSA
and VSSB Power Supply terminals are separate and independent from
VSS and may be more negative than the VSS ground reference termi-
nal. The use of level shifters in the gate drive circuitry to the NMOS
(low-side) output stages allows controlled level shifting of the output
drive relative to ground.
Ordering Information
PART NUMBER
HIP4020IB
TEMP.
RANGE (oC)
-40 to 85
PACKAGE
20 Ld SOIC
PKG. NO.
M20.3
Pinout
HIP4020 SOIC
TOP VIEW
NC 1
ILF 2
B2 3
ENB 4
B1 5
VSS 6
ENA 7
A1 8
A2 9
NC 10
20 NC
19 VDD
18 NC
17 OUTB
16 VSSB
15 VSSA
14 OUTA
13 NC
12 VDD
11 NC
Block Diagram
VDD
B1
B2
ENB
A1
A2
ENA
ILF
ISENSE
Q1
ISENSE
Q3
OUTB
Q2
ISENSE
TSENSE
OUTA
Q4
ISENSE
VSS
VSSA
VSSB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3976.1
1 page  
HIP4020
Application
The HIP4020 is designed to detect load current feedback from
sampling resistors of low value in the source connections of the
output drivers to VDD, VSSA and VSSB (See Figure 1). When the
sink or source current at OUTA or OUTB exceeds the preset
OC (Over-Current) limiting value of 550mA typical, the current
is held at the limiting value. If the OT (Over-Temperature) Shut-
down Protection limit is exceeded, temperature sensing BiMOS
circuits limit the junction temperature to 150oC typical.
The circuit of Figure 1 shows the Full H-Switch in a small motor-
drive application. The left (A) and right (B) H-Switch’s are con-
trolled from the A and B inputs via the A and B CONTROL
LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The
circuit is intended to safely start, stop, and control rotational
direction for a motor requiring no more than 0.5A of supply cur-
rent. The stop function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors Q1 and Q3
are OFF; which cuts-off supply current to OUTA and OUTB.
With the BRAKE terminal Low and ENABLE Inputs High, either
Q1 and Q4 or Q3 and Q2 will be driven into conduction by the
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor ter-
minal OUTA) at the moment of Dynamic Braking will con-
tinue to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
Q4 to the VSSB and VSSA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where VDD to VSS are the Power Supply reference terminals
for the Control Logic, the lowest practical supply voltage for
proper logic control should be no less than 2.0V. The VSSA
and VSSB terminals are separate and independent from VSS
and may be more negative than the VSS ground reference
terminal. However, the maximum supply level from VDD to
VSSA or VSSB must not be greater than the Absolute Maxi-
mum Supply Voltage rating.
Terminals A1, B1, A2, B2, ENA and ENB are internally con-
nected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level Con-
verters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV. How-
ever, these devices are sensitive to electrostatic discharge.
Proper I.C. handling procedures should be followed.
VDD
INPUT
LEVEL
CONV.
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
VDD
A1
(DIR)
A2
(BRAKE)
P-DR
LIMIT
OT AND OC
PROTECT
Q1
Q2
D1
OUTA
D2
ENA
(ENABLE)
N-DR
LIMIT
VSSA
VDD
B1
(DIR)
B2
(BRAKE)
P-DR
LIMIT
OT AND OC
PROTECT
Q3
Q4
D3
OUTB
D4
ENB
(ENABLE)
N-DR
LIMIT
VSSB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HIP4020.PDF ] | |
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