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PDF HIP2060 Data sheet ( Hoja de datos )

Número de pieza HIP2060
Descripción 60V/ 10A Half Bridge Power MOSFET Array
Fabricantes Intersil Corporation 
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HIP2060
April 1998
60V, 10A Half Bridge Power MOSFET Array
Features
Description
• Two 10A Power MOS N-Channel Transistors
• Output Voltage to 60V
• rDS(ON) . . . . . 0.135Max Per Transistor at VGS = 15V
• rDS(ON) . . . . . . 0.15Max Per Transistor at VGS = 10V
• Pulsed Current . . . . . . . . . . . . . . . . 25A Each Transistor
• Avalanche Energy . . . . . . . . . . 100mJ Each Transistor
• Grounded Tab Eliminates Heat Sink Isolation
Ordering Information
The HIP2060 is a power half-bridge MOSFET array that con-
sists of two matched N-Channel enhancement-mode MOS
transistors. The advanced Intersil PASIC2 process technol-
ogy used in this product utilizes efficient geometries that pro-
vides outstanding device performance and ruggedness.
The HIP2060 is designed to integrate two power devices in
one chip thus providing board layout area and heat sink sav-
ings for applications such as Motor Controls, Uninterruptable
Power Supplies, Switch Mode Power Supplies, Voice Coil
Motors, and Class D Power Amplifier.
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG.
NO.
HIP2060AS1
-40 to 125 5 Ld SIP
Z5.067C
HIP2060AS2
-40 to 125 5 Ld Gullwing SIP Z5.067A
HIP2060AS3
-40 to 125 5 Ld SIP
Z5.067B
NOTE: When ordering use the entire part number.
Symbol
DRAIN1 5
GATE1
1
Z1
GATE2
2
Z2
D1
SOURCE1 = DRAIN2
4
SOURCE2 3, TAB
Packages
JEDEC TS-001AA (ALTERNATE VERSION)
HIP2060 AS1
5432
1
(TAB)
Z5.067B (SIP)
HIP2060 AS3
JEDEC MO-169
HIP2060 AS2
1 GATE1
2 GATE2
3 SOURCE2
4 SOURCE1-DRAIN2
5 DRAIN1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3983.5

1 page




HIP2060 pdf
HIP2060
Typical Performance Curves (Continued)
2.0 16
VGS = VDS, ID = 250µA
1.5 12
1.0 8
VDS = 50V
VDS = 30V
VDS = 20V
ID = 10A, TC = 25oC
0.5 4
0
-75 -25 25 75 125
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION
TEMPERATURE
175
0
0 5 10 15 20
Q, GATE CHARGE (nC)
FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE
1000
800
600
400
200
VGS = 0V, f = 1MHz, TC = 25oC
CRSS
COSS (U)
COSS (L)
CISS
0
0 5 10 15 20
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 9. CAPACITANCE vs VOLTAGE
25
12
10
VGS = 15V
8 VGS = 10V
6
4
2
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
TC = 25oC
1 D = 1.0
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
10-5
10-4
10-3
NOTES:
1. DUTY FACTOR, D = t1/t2
2. PEAK TJ = PDM x (ZθJC) +TC
10-2
10-1
10o
101
t1, RECTANGULAR PULSE DURATION (s)
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
5

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