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HIP1012CB の電気的特性と機能

HIP1012CBのメーカーはIntersil Corporationです、この部品の機能は「Dual Power Distribution Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP1012CB
部品説明 Dual Power Distribution Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP1012CB Datasheet, HIP1012CB PDF,ピン配置, 機能
Data Sheet
HIP1012, HIP1012A
November 1999 File Number 4419.4
Dual Power Distribution Controller
The HIP1012 is a HOT SWAP dual supply power distribution
controller. Two external N-Channel MOSFETs are driven to
distribute power while providing load fault isolation.
At turn-on, the gate of each external N-Channel MOSFET is
charged with a 10µA current source. Capacitors on each
gate (see the Typical Application Diagram), create a
programmable ramp (soft turn-on) to control inrush currents.
A built in charge pump supplies the gate drive for the 12V
supply N-Channel MOSFET switch.
Over current protection is facilitated by two external current
sense resistors. When the current through either resistor
exceeds the user programmed value the controller enters the
current regulation mode. The time-out capacitor, CTIM, starts
charging as the controller enters the time out period. Once
CTIM charges to a 2V threshold, the N-Channel MOSFETs
are latched off. In the event of a fault at least three times the
current limit level, the N-Channel MOSFET gates are pulled
low immediately before entering time out period. The
controller is reset by a rising edge on either PWRON pin.
Choosing the voltage selection mode the HIP1012 controls
either +12V/5V or +3.3V/+5V supplies.
For those applications where voltage tolerance is a concern
the HIP1012A has a minimum nominal over current threshold
voltage of 50mV as compared to 100mV for the HIP1012.
Ordering Information
PART NUMBER
HIP1012CB
HIP1012ACB
HIP1012CB-T
HIP1012ACB-T
TEMP.
RANGE (oC)
PACKAGE
-0 to 70 14 Ld SOIC
-0 to 70 14 Ld SOIC
Tape and Reel
PKG.
NO.
M14.15
M14.15
Features
• HOT SWAP Dual Power Distribution Control for +5V and
+12V or +5V and +3.3V
• Provides Fault Isolation
• Programmable Current Regulation Level
• Programmable Time Out
• Charge Pump Allows the Use of N-Channel MOSFETs
• Power Good and Over Current Latch Indicators
• Enhanced Over Current Sensitivity Available
• Redundant Power On Controls
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Current Limit Detection Provide Fast
Response to Varying Fault Conditions
• Less Than 1µs Response Time to Dead Short
• 3µs Response Time to 200% Current Overshoot
Applications
• Redundant Array of Independent Disks (RAID) System
• Power Distribution Control
• Hot Plug™, Hot Swap Components
Pinout
HIP1012 (SOIC)
TOP VIEW
3/12VS 1
3/12VG 2
VDD
MODE/
PWRON1
PWRON2
5VG
3
4
5
6
5VS 7
14 3/12VISEN
13 RILIM
12 GND
11 CPUMP
10 CTIM
9 PGOOD
8 5VISEN
Typical Application Diagram
OPTIONAL
VDD RFILTER
CFILTER
CPUMP
RSENSE
12V
RGATE
HIP1012
CGATE
POWER ON
INPUTS
3/12VS3/12VISEN
3/12VG RILIM
VDD
GND
M/PON1 CPUMP
PWRON2 CTIM
5V
RGATE 5VG
PGOOD
5VS 5ISEN
CGATE
RSENSE
RLOAD
RILIM
CTIM
5V OR 3.3V
RLOAD
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Hot Plug™ is a trademark of Core International, Inc.

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HIP1012CB pdf, ピン配列
HIP1012, HIP1012A
Pin Descriptions
PIN # SYMBOL
FUNCTION
DESCRIPTION
1 3V/12VS 3.3 V/12V Source
Connect to source of associated external N-Channel MOSFET switch to sense output
voltage.
2 3V/12VG 3.3V/12V Gate
Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node
to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 17.4V by a 10µA
current source when in 5v/12V mode of operation, otherwise capacitor will be charged to
11.4V. A small resistor (10 - 200) should be placed in series with the gate capacitor to
ground to prevent current oscillations.
3
VDD
Chip Supply
Connect to 12V supply. This can be either connected directly to the +12V rail supplying the
load voltage or to a dedicated VDD +12V supply. If the former is chosen special attention to
VDD decoupling must be paid.
4 MODE/ Power ON/ Reset
PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on when
PWRON1 Invokes 3.3V operation either pin is driven low. After a current limit time out, the chip is reset by the rising edge of a
when shorted to VDD, pin 3. reset signal applied to either PWRON pin. Each input has 100µA pull up capability which is
compatible with 3V and 5V open drain and standard logic. PWRON1 is also used to invoke
5 PWRON2 Power ON/ Reset
3.3V control operation in preference to +12V control. By tying pin 4 to pin 3 the charge pump
is disabled and the UV threshold also shifts to 2.8V.
6
5VG
5V Gate
Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a 10µA
current source. A small resistor (10 - 200) should be placed in series with the gate
capacitor to ground to prevent current oscillations.
7 5VS 5V Source
Connect to the source side of 5V external N-Channel MOSFET switch to sense output
voltage.
8 5VISEN 5V Current Sense
Connect to the load side of the 5V sense resistor to measure the voltage drop across this
resistor between 5VS and 5VISEN pins.
9
PGOOD Power Good indicator
Indicates that all output voltages are within specification. PGOOD is driven by an open drain
N-Channel MOSFET. It is pulled low when any output is not within specification.
10
CTIM
Current Limit Timing
Connect a capacitor from this pin to ground. This capacitor controls the time between the
Capacitor
onset of current limit and chip shutdown (current limit time-out). The duration of current limit
time-out (in seconds) = 200kx CTIM (Farads).
11
CPUMP
Charge Pump
Capacitor
Connect a 0.1µF capacitor between this pin and VDD (pin3). Directly connect this pin to VDD
when in 3.3V control mode.
12
GND
Chip Ground
13
RILIM
Current Limit Set
Resistor
A resistor connected between this pin and ground determines the current level at which
current limit is activated. This current is determined by the ratio of the RILIM resistor to the
sense resistor (RSENSE). The current at current limit onset is equal to 10µA x (RILIM/
RSENSE). The HIP1012 is limited to a 10kmin value (OC Vth = 100mV) resistor whereas
the HIP1012A can accommodate a 5kresistor for a lower OC Vth (50mV).
14 3V/12VISEN 3.3V/12V Current Sense Connect to the load side of sense resistor to measure the voltage drop across this resistor.
3


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HIP1012CB 電子部品, 半導体
HIP1012, HIP1012A
TABLE 1.
RILIM RESISTOR
15k
NOMINAL OC VTH
150mV
10k
100mV
7.5k
75mV
4.99k
50mV
NOTE: Nominal OC Vth = Rilim x 10µA.
TABLE 2.
CTIM CAPACITOR
0.022µF
NOMINAL TIME OUT PERIOD
4.4ms
0.047µF
9.4ms
0.1µF
20ms
NOTE: Nominal time-out period in seconds = CTIM x 200kΩ.
The HIP1012 responds to a load short (defined as a current
level 3X the OC set point) immediately, driving the relevant
N-Channel MOSFET gate to 0V in less than 1µs. The gate
voltage is then slowly ramped up turning on the N-Channel
MOSFET to the programmed current limit level, this is the
start of the time out period. The programmed current level is
held until either the OC event passes or the time out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the CTIM charging current is
diverted away from the capacitor. If the time out period
expires prior to OC resolution then both gates are quickly
pulled to 0V turning off both N-Channel MOSFETs
simultaneously.
Upon any OC or UV condition the PGOOD signal will pull
low when tied high through a resistor to the logic supply. This
pin is a fault indicator but not the OC latch off indicator. For
an OC latch off indication, monitor CTIM, pin 10. This pin will
rise rapidly to 12V once the time out period expires. See
block diagram for OC latch off circuit suggestion.
The HIP1012 is reset by a rising edge on either PWRON pin
and is turned on by either PWRON pin being driven low. The
HIP1012 can control either +12V/5V or +3.3V/+5V supplies.
Tying the PWRON1 pin to VDD, invokes the +3.3V/+5V
voltage mode. In this mode, the external charge pump
capacitor is not needed and Cpump, pin 11 is also tied
directly to VDD.
HIP1012 Application Considerations
For Applications where voltage tolerances are of critical
concern the HIP1012A is better suited as it has a minimum
nominal OC Vth performance of 50mV verses 100mV with
the HIP1012 over the entire temperature range. This allows
the use of lower Rsense value resistors resulting in higher
efficiency.
When using the HIP1012 in the 12V and 5V mode
additional VDD decoupling may be necessary to prevent a
power on reset due to a sag on VDD pin upon an OC latch
off. The addition of a capacitor from VDD to GND may often
be adequate but a small value isolation resistor may also
be necessary. See the Simplified Schematic.
Current loop stabilization is facilitated through a small
value resistor in series with the gate timing capacitor. As the
HIP1012 drives a highly inductive current load, instability
characterized by the gate voltage repeatedly ramping up and
down may appear. A simple method to enhance stability is
provided by the substitution of a larger value gate resistor.
Typically this situation can be avoided by eliminating long
point to point wiring to the load.
Random resets may occur if the HIP1012 sense pins are
pulled below ground when turning off a highly inductive load.
Place a large load capacitor (10-50µF) on the output to
eliminate the unintended resets.
During the Time Out delay period with the HIP1012 in
current limit mode, the VGS of the external N-Channel
MOSFETs is reduced driving the N-Channel MOSFET switch
into a high rDS(ON) state. Thus avoid extended time out
periods as the external N-Channel MOSFETs may be
damaged or destroyed due to excessive internal power
dissipation. Refer to the MOSFET manufacturers data sheet
for SOA information.
With the high levels of inrush current e.g., highly capacitive
loads and motor start up currents, choosing the current
limiting level is crucial to provide both protection and still
allow for this inrush current without latching off. Consider this
in addition to the time out delay when choosing MOSFETs
for your design.
Physical layout of Rsense resistors is critical to avoid the
possibility of false over current occurrences. Ideally trace
routing between the Rsense resistors and the HIP1012 is
direct and as short as possible with zero current in the sense
lines. Refer to the demo boards for examples.
External Pull Down resistors (5k) from the xISEN pins to
ground will prevent the outputs from floating when the
external switch FETs are disabled and the outputs are open.
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部品番号部品説明メーカ
HIP1012CB

Dual Power Distribution Controller

Intersil Corporation
Intersil Corporation
HIP1012CB-T

Dual Power Distribution Controller

Intersil Corporation
Intersil Corporation


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