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PDF ISP1507C Data sheet ( Hoja de datos )
| Número de pieza | ISP1507C | |
| Descripción | (ISP1507C/D) ULPI Hi-Speed Universal Serial Bus host and peripheral transceiver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ISP1507C; ISP1507D
ULPI Hi-Speed Universal Serial Bus host and peripheral
transceiver
Rev. 01 — 28 May 2008
Product data sheet
1. General description
The ISP1507 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The ISP1507 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN24 package.
2. Features
I Fully complies with:
N Universal Serial Bus Specification Rev. 2.0
N UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I Interfaces to host and peripheral cores; optimized for stand-alone and embedded host
applications with an external VBUS supply; stand-alone peripheral cores, and Session
Request Protocol (SRP)-capable peripheral cores
I Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N USB clock and data recovery to receive USB data up to ±500 ppm
N Insertion of stuff bits during transmit and discarding of stuff bits during receive
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I Supports SRP for reduced power consumption
N Complete control over bus resistors
N Data line and VBUS pulsing session request methods
Free Datasheet http://www.datasheet4u.com/
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
ISP1507C; ISP1507D
ULPI HS USB host and peripheral transceiver
terminal 1
index area
DATA1
DATA0
VCC(I/O)
RREF
DM
DP
1
2
3
4
5
6
ISP1507
18 DATA6
17 DATA7
16 NXT
15 STP
14 DIR
13 REG1V8
004aab079
Transparent top view
Fig 2. Pin configuration HVQFN24; top view
6.2 Pin description
Table 2. Pin description
Symbol[1][2]
Pin Type[3]
DATA1
1 I/O
DATA0
2 I/O
VCC(I/O)
RREF
DM
DP
VCC
VBUS/FAULT
3P
4 AI/O
5 AI/O
6 AI/O
7P
8 AI/O
REG3V3
XTAL1
XTAL2
9P
10 AI
11 AO
Description[4]
pin 1 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
pin 0 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); plain input; programmable pull down
I/O supply rail
resistor reference
data minus (D−) pin of the USB cable
data plus (D+) pin of the USB cable
input supply voltage or battery source
This pin has two possible functions:
VBUS (analog input and output) — VBUS pin of the USB cable.
FAULT (input) — Input pin for the external VBUS digital overcurrent or fault detector
signal.
If this pin is not used as either VBUS or FAULT, it must be connected to ground.
5 V tolerant
3.3 V regulator output
crystal oscillator or clock input
crystal oscillator output
ISP1507C_ISP1507D_1
Product data sheet
Rev. 01 — 28 May 2008
© NXP B.V. 2008. All rights reserved.
5 of 74
Free Datasheet http://www.datasheet4u.com/
5 Page 
NXP Semiconductors
ISP1507C; ISP1507D
ULPI HS USB host and peripheral transceiver
7.10.7 REG3V3 and REG1V8
Regulator output voltage. These supplies are used to power the ISP1507 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you connect REG3V3 and
REG1V8 to decoupling capacitors. For an example, see Section 16.
7.10.8 XTAL1 and XTAL2
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1507 product version.
If the link requires a 60 MHz clock from the ISP1507, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see Section 16.
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1507 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
7.10.9 RESET_N/PSW_N
This pin provides two optional functions. If neither function is used, this pin must be
connected to VCC(I/O).
7.10.9.1 RESET_N
An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The
ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to VCC(I/O).
For details on using RESET_N, see Section 9.3.2.
7.10.9.2 PSW_N
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external VBUS switch or charge pump enable circuit to control the external VBUS
power source. An external pull-up resistor, Rpullup, is required when PSW_N is used. This
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see Section 16.
To use the PSW_N pin, the link must disable the reset input by setting the
IGNORE_RESET bit in the PWR_CTRL register (see Section 10.1.14) to logic 1. This will
ensure that PSW_N is not misinterpreted as a reset.
If the link is in host mode, it can enable the external VBUS power source by setting the
DRV_VBUS_EXT bit in the OTG_CTRL register (see Section 10.1.4) to logic 1. The
ISP1507 will drive PSW_N to LOW to enable the external VBUS power source. If the link
detects an overcurrent condition (the VBUS state in RXCMD is not 11b), it must disable the
external VBUS supply by setting DRV_VBUS_EXT to logic 0.
ISP1507C_ISP1507D_1
Product data sheet
Rev. 01 — 28 May 2008
© NXP B.V. 2008. All rights reserved.
11 of 74
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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