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PDF HIP0060 Data sheet ( Hoja de datos )

Número de pieza HIP0060
Descripción 1.5A/ 50V Quad Low Side Power Driver with Serial Bus Control and Fault Protection
Fabricantes Intersil Corporation 
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HIP0060
July 1997
1.5A, 50V Quad Low Side Power Driver
with Serial Bus Control and Fault Protection
Features
Description
• Quad NDMOS Output Drivers in a High Voltage Power
BiMOS Process
• Over-Stress Protection - Each Output
- Over-Current Limiting . . . . . . . . . . . . . . . . . .1.5A Min
- Internal Zener Drain-to-Gate Over-Voltage Clamp
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Typ
- Thermal Shutdown Protection
- Open-Load Detection
• Low Quiescent Current . . . . . . . . . . . . . . . . 10mA Max
• Serial Diagnostic Link with SPI Bus
• Diagnostic Interrupt Fault Flag
• 5V CMOS Logic Input Control
• Common Reset for Fault Bits and Output Drivers
• Ambient Operating
Temperature Range. . . . . . . . . . . . . . . . -40oC to 125oC
Applications
• Automotive and Industrial Systems
• Fuel Injection Drivers
• Solenoids, Relays and Lamp Drivers
• Logic and µP Controlled Drivers
• Robotic Controls
The HIP0060 is a 5V logic controlled Quad Low Side Power
Driver. The outputs are individually protected for over-current
(OC), over-temperature (OT) and over-voltage (OV). If an OC
short circuit in the output load is sensed (IS) in one output
power driver, that output current will be independently limited
while the other outputs remain in operation. Over-current is
limited by direct gate feedback. Over-voltage protection is pro-
vided by a drain-to-gate zener diode that clamps inductive
switching pulses.
The output drivers are individually controlled through a Gate
Control Latch. Temperature is sensed at each output. If a ther-
mal fault exists, a status flag is set and the output is latched
off. Open-load (OL) and over-temperature (OT) faults sets a
status flag bit as diagnostic output to the SPI bus. For all fault
bits (8), an ORed one-shot interrupt signal is output to the INT
pin. An RST reset clears the fault flags and disables all out-
puts while active. The Serial Peripheral Interface (SPI) bus
pins are the Serial Input (SI), Serial Output (SO), Serial Data
Clock (SCK) and the Chip Select (CS).
The HIP0060 is fabricated in a Power BiMOS IC process, and
is intended for use in automotive and other applications having
a wide range of temperature and electrical stress conditions. It
is particularly suited for driving lamps, relays, and solenoids in
applications where low operating power, high breakdown volt-
age, and higher output current at high temperatures is required.
Ordering Information
PART NUMBER
HIP0060AB
TEMP.
RANGE (oC)
PACKAGE
-40 to 125 24 Ld SOIC
PKG.
NO.
M24.3
Pinout
HIP0060 (SOIC)
TOP VIEW
GND 1
INT 2
INA 3
OUTA 4
GND 5
GND 6
GND 7
GND 8
OUTB 9
INB 10
SI 11
CS 12
24 VDD
23 RST
22 IND
21 OUTD
20 GND
19 GND
18 GND
17 GND
16 OUTC
15 INC
14 SO
13 SCK
Block Diagram
CHANNEL A
(1 OF 4)
VDD
+5V
GATE
CONTROL
INA LATCH
OPEN LOAD
DETECTOR
OVER TEMP.
DETECTOR
RST
SCK
SI
SO
CS
+
O.T.
BIT
O.L.
BIT
OVER
CURRENT
LIMIT
IS
8-BIT SPI
(SERIAL
DIAG.
REG)
TO
B, C, D
2
2
2
2 22
FROM B, C, D
8 ORed O.T./O.L.
FAULT INPUTS,
ONE-SHOT
MULTI OUTPUT
OUTA
INT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 4045

1 page




HIP0060 pdf
HIP0060
4.7k
5V, 100µs
50
2% DUTY CYCLE
FUNCTION GEN.
4.7k
RST
INA
+5V VDD
INB
HIP0060
INC (TIMING TEST
CIRCUIT)
IND
INT
OUTA
OUTB
OUTC
OUTD
GND
+14.5V
30
30
30
30
5V
VIN
0V
VOUT
14.5V
0V
3V
tON
90%
tr
10%
1V
tOFF
tf
90%
10%
FIGURE 2. INPUT TO OUTPUT SWITCHING TIME DIAGRAM FOR EACH SWITCHING CHANNEL. THE CONDITIONS SHOWN
REFER TO THE TIMING TEST CIRCUIT
10000
1000
100 SAFE OPERATING AREA
BELOW LINE
10
0.1
1 10
TIME (ms)
100
FIGURE 3. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, TA = 25oC
5

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