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PDF HIP0045AB Data sheet ( Hoja de datos )
| Número de pieza | HIP0045AB | |
| Descripción | 1A/50V Octal Low Side Power Driver With Serial Bus Control and Fault Protection | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HIP0045
April 1999 File Number 4047.2
1A/50V Octal Low Side Power Driver With
Serial Bus Control and Fault Protection
The HIP0045 is a logic controlled, eight channel Octal Serial
Power Low Side Driver. The serial peripheral interface (SPI)
utilized by the HIP0045 is a serial synchronous bus compatible
with Intersil CDP68HC05, or equivalent, microcomputers. As
shown in the Block Diagram for the HIP0045, each of the open
drain MOS Output Drivers have individual protection for over-
voltage and over-current. Each output channel has separate
output latch control with fault unlatch and diagnostic or status
feedback. Under normal ON conditions, each output driver is in
a low voltage, high current state of saturated turn-on.
Comparators in the diagnostic circuitry monitor the output
drivers to determine if an out of saturation condition exists. If a
fault is sensed, the respective output driver for Channels 0 - 5
have overcurrent latch-off. Channels 6 and 7 are configured for
lamp drivers and have current limiting with over-temperature
latch-off. Channels 0 and 1 have direct parallel drive control for
PWM applications and are ORed with the SPI Bus control. All
channels are SPI Bus controlled and sense the output states
for diagnostic feedback.
The HIP0045 is fabricated in a Power BiMOS IC process,
and is intended for use in automotive and other applications
having a wide range of temperature and electrical stress
conditions. It is particularly suited for driving relays,
solenoids and lamps in applications where low standby
power, high operating voltage, and high output current in
high ambient temperature conditions is required.
The HIP0045 is in a 20 lead plastic Power SOP (PSOP)
Package with an integral copper ‘slug’ to conduct heat directly
to a PCB interface or heat sink on the bottom of the package.
Ordering Information
PART NO. TEMP. RANGE (oC) PACKAGE
HIP0045AB
-40 to 125
20 Ld PSOP
PKG. NO.
M20.433
Driver Block Diagram
OUT
SPI AND
DIRECT
INPUT
CONTROL
WITH
FAULT/
STATUS
OUTPUT
DRIVER
OC LATCH
(CH. 0-5)
OC LIMIT
(CH. 6, 7)
-
+
ISK
VCC
OVER-TEMP.
DET. (CH. 6, 7)
OC
REF
+
-
VREF
RESET
FAULT/STATUS
Features
• Octal NDMOS Output Drivers in a High Voltage Power
BiMOS Process
• Over-Stress Protection - Each Output:
- Over-Current Protection . . . . . . . . . . . . . . . . . . . 1A Min
- Over-Voltage Clamp Protection . . . . . . . . . . . . 50V Typ
- Thermal Shutdown Protection (2 Channels)
• Open-Load Detection
• Power BiMOS Output Configuration
- Current Latch-Off Protection for 6 Channels; 2 with
External Drive Input and ORed with SPI Bus Control
- 2 Channels Configured for Lamp Drivers with Current
Limiting and Over-Temperature Latch-Off
• High Speed CMOS Logic Control
- SPI Bus Controlled Interface
- Individual Output Latch
- Individual Fault Unlatch and Feedback
- Common Reset Line
• Low Quiescent Current . . . . . . . . . . . . . . . . . . . 5mA Max
• Ambient Operating Temp. Range . . . . . . . -40oC to 125oC
Applications
• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
• Logic and µP Controlled Drivers
• Robotic Controls
Pinout
HIP0045 (PSOP WITH HEAT SLUG)
TOP VIEW
INTEGRAL COPPER
HEAT SINK ‘SLUG’
FOR PCB CONTACT
OR EXT. HEAT SINK
GND
IN0
MISO
OUT0
OUT2
OUT4
OUT6
MOSI
SCK
GND
1
2
3
4
5
6
7
8
9
10
20 GND
19 CE
18 RESET
17 OUT7
16 OUT5
15 OUT3
14 OUT1
13 VCC
12 IN1
11 GND
4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HIP0045
Serial Peripheral Interface Timing (MOSI, MISO Load Capacitor = 100pF, See Figure 1)
PARAMETER
SYMBOL
TEST CONDITION
MIN TYP MAX UNITS
Data Valid Time, SCK to Data at MISO Valid
Time for SCK Low before CE Low (SCK Setup Time
before CE High to Low Change)
tV VCC = 5V ±0.1V
tSCK_LEAD
- - 100 ns
100 -
- ns
Time for SCK High after CE High
CE Pulse Filter Time
tSCK_LAG
150 -
- Note 9
-
-
ns
ns
NOTES:
7. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the Output
Clamp Voltage, VOC.
8. The measurement of Output Leakage Current includes the Output Pull-Down Current, ISK. Each Output has a Current Pull-Down which is used
to detect open load fault conditions.
9. The digital filter time for the output latch function determines if the output latch function will be enabled. The output latch function will only be
enabled if a positive CE slope occurs after 8 SCK clock cycles or a multiple of 8 SCK cycles since the last CE negative slope change.
Timing Diagrams
CE
SCK
(CPOL = 0, CPHA = 1)
MSB 6 5 4 3
2 1 LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
CE
(INPUT)
tLEAD tWSCKH
SCK
(INPUT)
MISO
(OUTPUT)
HIGH
Z
LAST BIT
tWSCKL
TRANSMITTED
D7O
tEN tV
MOSI
(INPUT)
D7I
tSU tH
D6O
D6I
DRIVER
OUTPUT
OLD
tLAG
D0O
D0I
FIGURE 1B. SPI TIMING DIAGRAM
4-5
tDIS
FAULT-INDUCED
TURN-OFF
NEW
tDON
tDOFF
tDF
5 Page | ||
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| PDF Descargar | [ Datasheet HIP0045AB.PDF ] | |
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