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LC4384V-75TN176C の電気的特性と機能

LC4384V-75TN176CのメーカーはLattice Semiconductorです、この部品の機能は「Super Fast High Density PLDs」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC4384V-75TN176C
部品説明 Super Fast High Density PLDs
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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LC4384V-75TN176C Datasheet, LC4384V-75TN176C PDF,ピン配置, 機能
ispMACHTM 4000V/B/C/Z Family
3.3V/2.5V/1.8V In-System Programmable
January 2004
Coolest Power
SuperFASTTM High Density PLDs
Data Sheet
Features
C
TM
Broad Device Offering
• Multiple temperature range support
High Performance
• fMAX = 400MHz maximum operating frequency
• tPD = 2.5ns propagation delay
• Up to four global clock pins with programmable
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
– Automotive: -40 to 130°C junction (Tj)
clock polarity control
Easy System Integration
• Up to 80 PTs per output
• Superior solution for power sensitive consumer
applications
Ease of Design
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Enhanced macrocells with individual clock,
• Operation with 3.3V (4000V), 2.5V (4000B) or
reset, preset and clock enable controls
1.8V (4000C/Z) supplies
• Up to four global OE controls
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and ret
• Fast path, SpeedLockingTM Path, and wide-PT
interfaces
• Hot-socketing
• Open-drain capability
path • Input pull-up, pull-down or bus-keeper
• Wide input gating (36 input logic blocks) for fast
• Programmable output slew rate
counters, state machines and address decoders
• 3.3V PCI compatible
Zero Power (ispMACH 4000Z) and Low
• IEEE 1149.1 boundary scan testable
Power (ispMACH 4000V/B/C)
• 3.3V/2.5V/1.8V In-System Programmable
• Typical static current 10µA (4032Z)
(ISP™) using IEEE 1532 compliant interface
• Typical static current 1.3mA (4000C)
• I/O pins with fast setup path
• 1.8V core low dynamic power
• Lead-free package options
• ispMACH 4000Z operational down to 1.6V VCC
Table 1. ispMACH 4000V/B/C Family Selection Guide
Macrocells
I/O + Dedicated
Inputs
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
Pins/Package
ispMACH
4032V/B/C
32
30+2/32+4
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30+2/32+4/
64+10
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64+10/92+4/
96+4
2.7
1.8
2.7
333
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP1
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O congurations.
ispMACH
4256V/B/C
256
64+10/96+14/
128+4/160+4
3.0
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
144 TQFP1
176 TQFP
256 fpBGA2
ispMACH
4384V/B/C
384
128+4/192+4
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
3.5
2.0
2.7
322
3.3/2.5/1.8V
176 TQFP
256 fpBGA
176 TQFP
256 fpBGA
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
1
ispm4k_20z

1 Page





LC4384V-75TN176C pdf, ピン配列
Lattice Semiconductor
Figure 1. Functional Block Diagram
ispMACH 4000V/B/C/Z Family Data Sheet
I/O
Block
Generic
ORP 16 Logic
Block
16
36
16
36
Generic
Logic 16
Block
ORP
I/O
Block
I/O
Block
Generic
ORP 16 Logic
Block
16
36
16
36
Generic
Logic 16
Block
ORP
I/O
Block
The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-
patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specied within an I/O bank that is con-
nected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
ispMACH 4000 Architecture
There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has
36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be
connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still
must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and
predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-
ated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-
pled from macrocells through the ORP. Figure 2 illustrates the GLB.
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3Pages


LC4384V-75TN176C 電子部品, 半導体
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Product Term Allocator
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 3 shows the available functions for each of the ve product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.
Table 3. Individual PT Steering
Product Term
PTn
PTn+1
PTn+2
PTn+3
PTn+4
Logic
Logic PT
Logic PT
Logic PT
Logic PT
Logic PT
Control
Single PT for XOR/OR
Individual Clock (PT Clock)
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
Individual Initialization (PT Initialization)
Individual OE (PTOE)
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 4. Available Clusters for Each Macrocell
Macrocell
Available Clusters
M0 — C0 C1 C2
M1 C0 C1 C2 C3
M2 C1 C2 C3 C4
M3 C2 C3 C4 C5
M4 C3 C4 C5 C6
M5 C4 C5 C6 C7
M6 C5 C6 C7 C8
M7 C6 C7 C8 C9
M8 C7 C8 C9 C10
M9 C8 C9 C10 C11
M10 C9 C10 C11 C12
M11 C10 C11 C12 C13
M12 C11 C12 C13 C14
M13 C12 C13 C14 C15
M14
C13 C14 C15
M15
C14 C15
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term
chains.
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部品番号部品説明メーカ
LC4384V-75TN176C

Super Fast High Density PLDs

Lattice Semiconductor
Lattice Semiconductor
LC4384V-75TN176I

Super Fast High Density PLDs

Lattice Semiconductor
Lattice Semiconductor


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