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39VF200A の電気的特性と機能

39VF200AのメーカーはSSTです、この部品の機能は「SST39VF200A」です。


製品の詳細 ( Datasheet PDF )

部品番号 39VF200A
部品説明 SST39VF200A
メーカ SST
ロゴ SST ロゴ 




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39VF200A Datasheet, 39VF200A PDF,ピン配置, 機能
2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories
FEATURES:
Data Sheet
• Organized as 128K x16 / 256K x16 / 512K x16
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF200A/400A/800A
– 2.7-3.6V for SST39VF200A/400A/800A
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 55 ns for SST39LF200A/400A/800A
– 70 ns for SST39VF200A/400A/800A
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39LF/VF200A
4 seconds (typical) for SST39LF/VF400A
8 seconds (typical) for SST39LF/VF800A
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
– 48-bump XFLGA (4mm x 6mm) – 4 and 8Mbit
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are 128K x16 / 256K x16 / 512K x16 CMOS
Multi-Purpose Flash (MPF) manufactured with SST propri-
etary, high-performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF200A/400A/800A
write (Program or Erase) with a 3.0-3.6V power supply.
The SST39VF200A/400A/800A write (Program or Erase)
with a 2.7-3.6V power supply. These devices conform to
JEDEC standard pinouts for x16 memories.
Featuring high-performance Word-Program, the
SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices provide a typical Word-Program time of 14
µsec. The devices use Toggle Bit or Data# Polling to detect
the completion of the Program or Erase operation. To pro-
tect against inadvertent write, they have on-chip hardware
and software data protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
©2010 Silicon Storage Technology, Inc.
S71117-12-000
04/10
1
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, they
significantly improve performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. When programming a flash device, the total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Free Datasheet http://www.datasheet4u.com/

1 Page





39VF200A pdf, ピン配列
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ7)
When the SST39LF200A/400A/800A and SST39VF200A/
400A/800A are in the internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. Note that even though DQ7 may
have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear
in subsequent successive Read cycles after an interval of
1 µs. During internal Erase operation, any attempt to read
DQ7 will produce a ‘0’. Once the internal Erase operation
is completed, DQ7 will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 8 for Data# Polling timing diagram
and Figure 19 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle
Bit timing diagram and Figure 19 for a flowchart.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide both hardware and software features to pro-
tect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide the JEDEC approved Software Data Protec-
tion scheme for all data alteration operations, i.e., Program
and Erase. Any Program operation requires the inclusion of
the three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte sequence. This group of
devices are shipped with the Software Data Protection per-
manently enabled. See Table 4 for the specific software
command codes. During SDP command sequence, invalid
commands will abort the device to Read mode within TRC.
The contents of DQ15-DQ8 can be VIL or VIH, but no other
value, during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A also contain the CFI information to describe the char-
acteristics of the device. In order to enter the CFI Query
mode, the system must write three-byte sequence, same
as Software ID Entry command with 98H (CFI Query com-
mand) to address 5555H in the last byte sequence. Once
the device enters the CFI Query mode, the system can
read CFI data at the addresses given in Tables 5 through 9.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
©2010 Silicon Storage Technology, Inc.
3
S71117-12-000
04/10
Free Datasheet http://www.datasheet4u.com/


3Pages


39VF200A 電子部品, 半導体
Data Sheet
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
TOP VIEW (balls facing down)
SST39VF200A
6
A2 A4 A6 NC NC NC WE# NC A9 A11
5
A1 A3 A7 NC
NC A10 A13 A14
4
A0 A5 NC
3
A8 A12 A15
CE# DQ8 DQ10
2
DQ4 DQ11 A16
VSS OE# DQ9 NC
1
NC DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
AB C D E F G H J K L
TOP VIEW (balls facing down)
SST39LF/VF400A
6
A2 A4 A6 A17 NC NC WE# NC A9 A11
5
A1 A3 A7 NC
NC A10 A13 A14
4
A0 A5 NC
3
A8 A12 A15
CE# DQ8 DQ10
2
DQ4 DQ11 A16
VSS OE# DQ9 NC
1
NC DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
AB C D E F G H J K L
TOP VIEW (balls facing down)
SST39LF/VF800A
6
A2 A4 A6 A17 NC NC WE# NC A9 A11
5
A1 A3 A7 NC
NC A10 A13 A14
4
A0 A5 A18
3
A8 A12 A15
CE# DQ8 DQ10
2
DQ4 DQ11 A16
VSS OE# DQ9 NC
1
NC DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
AB C D E F G H J K L
FIGURE 4: Pin Assignments for 48-Ball WFBGA and 48-Bump XFLGA
©2010 Silicon Storage Technology, Inc.
6
S71117-12-000
04/10
Free Datasheet http://www.datasheet4u.com/

6 Page



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部品番号部品説明メーカ
39VF200A

SST39VF200A

SST
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