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PDF ADP151 Data sheet ( Hoja de datos )
| Número de pieza | ADP151 | |
| Descripción | CMOS Linear Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Ultralow noise: 9 µV rms
No noise bypass capacitor required
Stable with 1 µF ceramic input and output capacitors
Maximum output current: 200 mA
Input voltage range: 2.2 V to 5.5 V
Low quiescent current
IGND = 10 µA with 0 load
IGND = 265 μA with 200 mA load
Low shutdown current: <1 µA
Low dropout voltage: 140 mV at 200 mA load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2.5%
16 fixed output voltage options: 1.1 V to 3.3 V
PSRR performance of 70 dB at 10 kHz
Current-limit and thermal overload protection
Logic controlled enable
Internal pull-down resistor on EN input
5-lead TSOT package
6-lead LFCSP package
4-ball, 0.4 mm pitch WLCSP
APPLICATIONS
RF, VCO, and PLL power supplies
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
GENERAL DESCRIPTION
The ADP151 is an ultralow noise, low dropout linear regulator
that operates from 2.2 V to 5.5 V and provides up to 200 mA
of output current. The low 140 mV dropout voltage at 200 mA
load improves efficiency and allows operation over a wide input
voltage range.
Using an innovative circuit topology, the ADP151 achieves
ultralow noise performance without the necessity of a bypass
capacitor, making it ideal for noise-sensitive analog and RF
applications. The ADP151 also achieves ultralow noise per-
formance without compromising PSRR or transient line and
load performance. The low 265 μA of quiescent current at
200 mA load makes the ADP151 suitable for battery-operated
portable equipment.
The ADP151 also includes an internal pull-down resistor on the
EN input.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Ultralow Noise, 200 mA,
CMOS Linear Regulator
ADP151
TYPICAL APPLICATION CIRCUIT
VIN = 2.3V
1µF
1 VIN VOUT 5
2 GND
VOUT = 1.8V
1µF
ON
OFF
3 EN
NC 4
NC = NO CONNECT
Figure 1. TSOT ADP151 with Fixed Output Voltage, 1.8 V
VIN = 2.3V
CIN
ON
OFF
12
VIN VOUT
TOP VIEW
(Not to Scale)
VOUT = 1.8V
A COUT
1µF
EN GND B
Figure 2. WLCSP ADP151 with Fixed Output Voltage, 1.8 V
VIN = 2.3V 6
VIN
1 VOUT = 1.8V
VOUT
1µF
ON
OFF
5
ADP151
NC TOP VIEW NC
2
4
(Not to Scale)
EN GND
3
1µF
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
Figure 3. LFCSP ADP151 with Fixed Output Voltage, 1.8 V
The ADP151 is specifically designed for stable operation with
tiny 1 µF, ±30% ceramic input and output capacitors to meet
the requirements of high performance, space constrained
applications.
The ADP151 is capable of 16 fixed output voltage options,
ranging from 1.1 V to 3.3 V.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP151 is available in tiny
5-lead TSOT, 6-lead LFCSP, and 4-ball, 0.4 mm pitch, halide-free
WLCSP packages for the smallest footprint solution to meet a
variety of portable power application requirements.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to +6.5V
−65°C to +150°C
−40°C to +125°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP151 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
The maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
ADP151
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information
on the board construction. For additional information, see the
AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale
Package, available at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
6-Lead 2 mm × 2 mm LFCSP
θJA ΨJB Unit
170 43 °C/W
260 58 °C/W
63.6 28.3 °C/W
ESD CAUTION
Rev. E | Page 5 of 24
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
THEORY OF OPERATION
The ADP151 is an ultralow noise, low quiescent current, low
dropout linear regulator that operates from 2.2 V to 5.5 V and
can provide up to 200 mA of output current. Drawing a low
265 μA of quiescent current (typical) at full load makes the
ADP151 ideal for battery-operated portable equipment.
Shutdown current consumption is typically 200 nA.
Using new innovative design techniques, the ADP151 provides
superior noise performance for noise-sensitive analog and RF
applications without the need for a noise bypass capacitor. The
ADP151 is also optimized for use with small 1 µF ceramic
capacitors.
VIN VOUT
GND
SHORT-CIRCUIT,
UVLO, AND
THERMAL
PROTECT
R1
EN SHUTDOWN
REN
REFERENCE
R2
Figure 27. Internal Block Diagram
ADP151
Internally, the ADP151 consists of a reference, an error amplifier, a
feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
An internal pull-down resistor on the EN input holds the input
low when the pin is left open.
The ADP151 is available in 16 output voltage options, ranging
from 1.1 V to 3.3 V. The ADP151 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on; when EN is low, VOUT turns off.
For automatic startup, EN can be tied to VIN.
Rev. E | Page 11 of 24
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADP151.PDF ] | |
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