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PDF ISL8036A Data sheet ( Hoja de datos )

Número de pieza ISL8036A
Descripción Dual 3A 1MHz/2.5MHz High Efficiency Synchronous Buck Regulator
Fabricantes Intersil 
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Dual 3A 1MHz/2.5MHz High Efficiency Synchronous
Buck Regulator
ISL8036, ISL8036A
ISL8036, ISL8036A are integrated power controllers
rated for dual 3A output current or current sharing
operation with a 1MHz (ISL8036)/2.5MHz (ISL8036A)
step-down regulator, which is ideal for any low power
low-voltage applications. The channels are 180°
out-of-phase for input RMS current and EMI reduction. It
is optimized for generating low output voltages down to
0.8V each. The supply voltage range is from 2.8V to 6V,
allowing for the use of a single Li+ cell, three NiMH cells
or a regulated 5V input. The two channels are 180
degrees out of phase, and each one has a guaranteed
minimum output current of 3A. They can be combined to
form a single 6A output in the current sharing mode.
While in current sharing, the interleaved PWM signals
reduce input and output ripple.
The ISL8036, ISL8036A includes a pair of low
ON-resistance P-channel and N-channel internal
MOSFETs to maximize efficiency and minimize external
component count. 100% duty-cycle operation allows less
than 250mV dropout voltage at 3A each.
The ISL8036, ISL8036A offers an independent 1ms
Power-good (PG) timer at power-up. When shutdown,
ISL8036, ISL8036A discharges the output capacitor.
Other features include internal digital soft-start, enable
for power sequence, overcurrent protection, and thermal
shutdown.
The ISL8036, ISL8036A is offered in a 24 Ld 4mmx4mm
QFN package with 1mm maximum height. The complete
converter occupies less than 1.5cm2 area.
Features
• 3A High Efficiency Synchronous Buck Regulator with
up to 95% Efficiency
• 2% Output Accuracy Over-Temperature/Load/Line
• Internal Digital Soft-Start - 1.5ms
• 6A Current Sharing Mode Operation
• External Synchronization up to 6MHz
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short Circuit
Protection
• Reverse Overcurrent Protection
Applications*(see page 24)
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Test and Measurement Systems
• Li-ion Battery Power Devices
• Bar Code Reader
Efficiency Characteristics Curve
100
90
80 3.3VOUT- PWM
70
60
50
40
0123456
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD, 1MHz 5VIN PWM, TA = +25°C
October 18, 2010
FN6853.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Free Datasheet http://www.datasheet4u.com/

1 page




ISL8036A pdf
Pin Configuration
ISL8036, ISL8036A
ISL8036, ISL8036A
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
LX2 1
18 LX1
VIN2 2
17 VIN1
VIN2 3
EN2 4
25
PAD
16 VIN1
15 VDD
PG2 5
14 SS
FB2 6
13 EN1
7 8 9 10 11 12
Pin Descriptions
PIN
NUMBER
1, 24
22, 23
4
5
6
7
8
9
10
11
12
13
SYMBOL
LX2
PGND2
EN2
PG2
FB2
COMP
NC
FB1
SGND
PG1
SYNC
EN1
DESCRIPTION
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Negative supply for the power stage of Channel 2.
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the
VOUT2 and discharge output capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
VOUT2 voltage.
The feedback network of the Channel 2 regulator. To be connected to FB1 (current sharing)
An additional external network across COMP and SGND is required to improve the loop compensation
of the amplifier channel parallel operation. The soft-start pin should be tied to the external capacitor.
No connect pin; please tie to GND.
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance
error amplifier. The output voltage is set by an external resistor divider connected to FB1. With a
properly selected divider, the output voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.8V reference. There is an internal compensation to meet a
typical application. In addition, the regulator power-good and undervoltage protection circuitry use
FB1 to monitor the Channel 1 regulator output voltage.
System ground.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
VOUT1 voltage.
Connect to logic high or input voltage VIN . Connect to an external function generator for external
Synchronization. Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or
to SGND).
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the
VOUT1 and discharge output capacitor when driven to low. Do not leave this pin floating.
5 FN6853.1
October 18, 2010
Free Datasheet http://www.datasheet4u.com/

5 Page





ISL8036A arduino
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: VOUT1 = 1.8V; VOUT2 = 0.8V; IOUT1 = 0A to 3A; IOUT2 = 0A to 3A,
FSW = 1MHz. (Continued)
LX2 2V/DIV
LX1 2V/DIV
VOUT2 RIPPLE 20mV/DIV
IL2 0.5A/DIV
VOUT RIPPLE 20mV/DIV
IL1 2A/DIV
FIGURE 10. STEADY STATE OPERATION AT NO LOAD
CHANNEL 2
FIGURE 11. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 1
LX2 2V/DIV
VOUT RIPPLE 50mV/DIV
VOUT RIPPLE 20mV/DIV
IL2 2A/DIV
FIGURE 12. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 2
IL1 2A/DIV
FIGURE 13. LOAD TRANSIENT CHANNEL 1
VOUT2 RIPPLE 20mV/DIV
IL2 2A/DIV
FIGURE 14. LOAD TRANSIENT CHANNEL 2
11
EN1 2V/DIV
VOUT 1V/DIV
IL1 0.5A/DIV
PG1 5V/DIV
FIGURE 15. SOFT-START WITH NO LOAD CHANNEL 1
FN6853.1
October 18, 2010
Free Datasheet http://www.datasheet4u.com/

11 Page







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