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PDF ADM1069 Data sheet ( Hoja de datos )
| Número de pieza | ADM1069 | |
| Descripción | Super Sequencer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Super Sequencer with Margining Control
ADM1069
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 4 voltage rails
4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP and 40-lead,
6 mm × 6 mm LFCSP packages
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
FUNCTIONAL BLOCK DIAGRAM
REFIN REFOUT REFGND SDA SCL A1 A0
ADM1069
VREF
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
SMBus
INTERFACE
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
VOUT VOUT VOUT VOUT
DAC DAC DAC DAC
VDD
ARBITRATOR
PDOGND
VDDCA P
DAC1 DAC2 DAC3 DAC4
VCCP
Figure 1.
GND
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1069 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1069 integrates a 12-bit analog-to-
digital converter (ADC) and four 8-bit voltage output digital-to-
analog converters (DACs). These circuits can implement a closed-
loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
For more information about the ADM1069 register map, refer
to the AN-721 Application Note.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADM1069
Data Sheet
Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at −5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.
The device also provides up to eight programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-
window faults on up to eight supplies. In addition, there are eight
programmable outputs that can be used as logic enables. Six of
these programmable outputs can also provide up to a 12 V output
for driving the gate of an N-FET that can be placed in the path
of a supply.
The logical core of the device is a sequencing engine (SE). This
state machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs, based
on the condition of the inputs.
The ADM1069 is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
REFIN
REFOUT
REFGND SDA SCL A1 A0
ADM1069
VREF
SMBus
INTERFACE
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
VDDCAP
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
VDD
ARBITRATOR
12-BIT
SAR ADC
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
DEVICE
CONTROLLER
OSC
EEPROM
CONFIGURABLE
OUTPUT DRIVER
(HV)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO7
SFD
REG 5.25V
CHARGE PUMP
VOUT
DAC
CONFIGURABLE
OUTPUT DRIVER
(LV)
VOUT
DAC
PDO8
PDOGND
GND
VCCP
DAC1 DAC2 DAC3 DAC4
Figure 2.
Rev. E | Page 4 of 34
5 Page 
ADM1069
Data Sheet
Pin No.
32-Lead 40-Lead
LQFP
LFCSP
31 39
32
N/A2
40
Mnemonic
VDDCAP
GND1
EPAD
Description
Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.
Note that a capacitor must be connected between this pin and GND. A 10 µF capacitor is recom-
mended for this purpose.
Supply Ground.
The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad
must be soldered to the board for improved mechanical stability.
1 In a typical application, all ground pins are connected together.
2 N/A means not applicable.
Rev. E | Page 10 of 34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADM1069.PDF ] | |
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