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UPD5753T7G の電気的特性と機能

UPD5753T7GのメーカーはRenesasです、この部品の機能は「SiGe BiCMOS Integrated Circuit」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD5753T7G
部品説明 SiGe BiCMOS Integrated Circuit
メーカ Renesas
ロゴ Renesas ロゴ 




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UPD5753T7G Datasheet, UPD5753T7G PDF,ピン配置, 機能
PreliminaryData Sheet
μPD5753T7G
SiGe/CMOS Integrated Circuit
4 × 2 IF Switch Matrix with Tone/Voltage Controller
R09DS0014EJ0100
Rev.1.00
Feb 22, 2011
FEATURES
4 independent IF channels, integral switching to channel input to either channel output
4 × 2 switch matrix with integrated switch control - Tone/Voltage
- Switch’s Enable/Disable function is linked with POLA input voltage level
Switch’s Enable condition : VPOLA > 9.5 V
Frequency range
: f = 250 MHz to 2150 MHz
High isolation
: ISLD/U = 33 dB TYP. @Worst mode
Insertion loss
: LINS = 7 dB TYP. @ ZS = ZL = 50 Ω
Insertion loss flatness
: ΔLINS = 1.0 dB TYP.
20-pin 4 × 4 mm square micro lead package ( 20-pin plastic QFN (0.5 mm pitch))
APPLICATIONS
DBS IF switching
Multiswitch, Switch box
4 × 2 switching application for microwave signal
ORDERING INFORMATION
Part Number
Order Number
Package
Marking
Supplying Form
μPD5753T7G-E1
μPD5753T7G-E1-A 20-pin plastic QFN
(0.5 mm pitch)
(Pb-Free)
D5753
Embossed tape 12 mm wide
Pin 6 to 10 face the perforation side of the tape
Qty 5 kpcs/reel
Dry packing specification (MSL 3 Equivalent)
Remark To order evaluation samples, please contact your nearby sales office.
Part number for sample order: μPD5753T7G
CAUTION
Observe precautions when handling because these devices are sensitive to electrostatic discharge.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 1 of 13
Free Datasheet http://www.datasheet4u.com/

1 Page





UPD5753T7G pdf, ピン配列
μPD5753T7G
STANDARD CHARACTERISTICS FOR REFERENCE
(TA = +25°C, VDD = +3.3 V, ZS = ZL = 50 Ω for each port, Worst mode, unless otherwise
specified)
Parameter
Symbol
Test Conditions
Reference Value
Unit
Insertion Loss Flatness
Isolation D/U Ratio 1 Note
Input Return Loss 1
Input Return Loss 2
POLA Control Current
POLA Switching Time
TONE Switching Time
ΔLINS
ISLD/U1
RLin1
RLin2
IPOLA
TPOLA
TTONE
|LINS1-LINS2|
Pin = 0 dBm, f = 0.95 GHz
Pin = 0 dBm, f = 0.95 GHz
Pin = 0 dBm, f = 2.15 GHz
VPOLA = 21 V
VPOLA = 18 V, OFF to ON
fTONE = 22 kHz, Duty Cycle = 50%,
pulse wave, VTONE = 600 mVp-p,
OFF to ON
1.0 dB
40 dB
20 dB
14 dB
230 μA
0.75 μs
220 μs
Note: Isolation D/U (Desire/Un-desire) ratio = (Signal Leakage (off-state)) (Insertion loss (on-state))at Worst mode
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 3 of 13
Free Datasheet http://www.datasheet4u.com/


3Pages


UPD5753T7G 電子部品, 半導体
μPD5753T7G
FUNCTIONAL DIAGRAM
6
IN-B
GND
GND
GND
IN-D
10
5
11
(Top View)
1
Enable1
Switch
Controller
Enable2
20
OUT1
M0
VDD
M1
OUT2
16
15
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 6 of 13
Free Datasheet http://www.datasheet4u.com/

6 Page



ページ 合計 : 15 ページ
 
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共有リンク

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部品番号部品説明メーカ
UPD5753T7G

SiGe BiCMOS Integrated Circuit

Renesas
Renesas


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