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AD9129 の電気的特性と機能

AD9129のメーカーはAnalog Devicesです、この部品の機能は「(AD9119 / AD9129) RF Digital-to-Analog Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9129
部品説明 (AD9119 / AD9129) RF Digital-to-Analog Converter
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9129 Datasheet, AD9129 PDF,ピン配置, 機能
Data Sheet
FEATURES
DAC update rate: up to 5.6 GSPS
Direct RF synthesis at 2.8 GSPS data rate
DC to 1.4 GHz in baseband mode
DC to 1.0 GHz in 2× interpolation mode
1.4 GHz to 4.2 GHz in Mix-Mode
Bypassable 2× interpolation
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
8 QAM carriers: ACLR > 65 dBc
Industry-leading single/multicarrier IF or RF synthesis
4-carrier W-CDMA ACLR at 2457.6 MSPS
fOUT = 900 MHz, ACLR = 71 dBc (baseband mode)
fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode)
fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode)
Dual-port LVDS and DHSTL data interface
Up to 1.4 GSPS operation
Source synchronous DDR clocking with parity bit
Low power: 1.0 W at 2.8 GSPS (1.3 W at 5.6 GSPS)
APPLICATIONS
Broadband communications systems
CMTS/VOD
Wireless infrastructure: W-CDMA, LTE, point-to-point
Instrumentation, automatic test equipment (ATE)
Radars, jammers
GENERAL DESCRIPTION
The AD9119/AD9129 are high performance, 11-/14-bit RF digital-
to-analog converters (DACs) supporting data rates up to 2.8 GSPS.
The DAC core is based on a quad-switch architecture that enables
dual-edge clocking operation, effectively increasing the DAC
update rate to 5.6 GSPS when configured for Mix-Mode™ or 2×
interpolation. The high dynamic range and bandwidth enable
multicarrier generation up to 4.2 GHz.
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the AD9119/AD9129 can reconstruct
RF carriers in the second and third Nyquist zone while still
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
current can be programmed over a range of 9.5 mA to 34.4 mA.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
11-/14-Bit, 5.6 GSPS,
RF Digital-to-Analog Converter
AD9119/AD9129
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
I250U VREF
SDIO
SDO
CS
SCLK
FRM_x
(FRAME/
PARITY)
P0_D[13:0]P,
P0_D[13:0]N
DCI_x
SPI
DLL
AD9129
1.2V
MIX-
NORMAL MODE
BASEBAND
MODE
Tx DAC
CORE
IOUTP
IOUTN
P1_D[13:0]P,
P1_D[13:0]N
PLL
DCO_x
CLOCK
DISTRIBUTION
Figure 1.
DCR
DACCLK_x
The AD9119/AD9129 include several features that may further
simplify system integration. A dual-port, source synchronous
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
are used to optimize timing between different clock domains.
A serial peripheral interface (SPI) is used to configure the
AD9119/AD9129 and monitor the status of readback registers.
The AD9119/AD9129 is manufactured on a 0.18 µm CMOS
process and operates from +1.8 V and −1.5 V supplies. It is
supplied in a 160-ball chip scale package ball grid array.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
support RF signal synthesis of up to 4.2 GHz.
2. Dual-port interface with double data rate (DDR) LVDS
data receivers supports 2800 MSPS maximum conversion rate.
3. Manufactured on a CMOS process; a proprietary switching
technique enhances dynamic performance.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/

1 Page





AD9129 pdf, ピン配列
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current Maximum
Full-Scale Output Current Minimum
Output Compliance Range
Output Impedance1
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
VSSA
DIGITAL SUPPLY VOLTAGES
VDD
FIR40 Enabled, DACCLK > 2600 MSPS
SUPPLY CURRENTS AND POWER DISSIPATION, 2.3 GSPS
(NORMAL MODE)
IVDDA
IVSSA
IDVDD
Power Dissipation
Normal Mode
FIR25 Enabled
FIR40 Enabled
Reduced Power Mode, Power-Down Enabled
(Register 0x01 = 0xEF)
IVDDA
IVSSA
IVDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.8 GSPS
(NORMAL MODE)
IVDDA
IVSSA
IDVDD
Power Dissipation (Normal Mode)
Min
33.4
9.1
1.5
0.4
1.70
−1.4
1.70
1.8
AD9119
Typ
11
0.2
0.15
+2.5
34.2
9.4
1
1.2
60
20
1.0
5
1.80
−1.5
1.8
1.9
202
53
307
1.0
1.17
1.3
7.6
6
0.4
230
53
336
1.1
1 For more information about output impedance, see the Output Stage Configuration section.
Rev. 0 | Page 3 of 68
Max
34.9
9.6
2.5
2
1.90
−1.6
1.90
2.0
209
54
327
1.05
1.24
1.4
AD9119/AD9129
AD9129
Min Typ Max Unit
14 Bits
1.4 LSB
1.1 LSB
+2.5 %
33.4 34.2 34.9 mA
9.1 9.4 9.6 mA
1.5 2.5 V
0.4 1
2V
1.2 V
60 ppm/°C
20 ppm/°C
1.0 V
5 kΩ
1.70 1.80 1.90 V
−1.4 −1.5 −1.6 V
1.70 1.8
1.8 1.9
1.90 V
2.0 V
202 209 mA
53 54 mA
307 327 mA
1.0 1.05 W
1.17 1.24 W
1.3 1.4 W
7.6 mA
6 µA
0.4 mA
230 mA
53 mA
336 mA
1.1 W
Free Datasheet http://www.datasheet4u.com/


3Pages


AD9129 電子部品, 半導体
AD9119/AD9129
Data Sheet
AC SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
DYNAMIC PERFORMANCE
DAC Update Rate (DACCLK_x Inputs)
Normal Mode, FIR25 Enabled, or FIR40 Enabled with VDD = 1.9 V
FIR40 Filter Enabled, VDD = 1.8 V
Adjusted DAC Update Rate1
Output Settling Time to 0.1%
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 2600 MSPS
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 2600 MSPS, fOUT2 = fOUT1 + 1.4 MHz
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
NOISE SPECTRAL DENSITY (NSD)
Single Tone, fDAC = 2800 MSPS
fOUT = 100 MHz
fOUT = 350MHz
fOUT = 550 MHz
fOUT = 850 MHz
DOCSIS ACLR PERFORMANCE (50 MHz to 1000 MHz) at ≥6 MHz OFFSET
fDAC = 2782 MSPS
8 Contiguous Carriers
16 Contiguous Carriers
32 Contiguous Carriers
W-CDMA ACLR (SINGLE CARRIER)
Adjacent Channel
fDAC = 2605.056 MSPS, fOUT = 750 MHz
fDAC= 2605.056 MSPS, fOUT = 950 MHz
fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode)
fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode)
Alternate Adjacent Channel
fDAC = 2605.056 MSPS, fOUT = 750 MHz
fDAC = 2605.056 MSPS, fOUT = 950 MHz
fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode)
fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode)
AD9119
AD9129
Min Typ Max Min Typ Max
1400
1400
1400
13
2800
2600
2800
1400
1400
1400
13
2800
2600
2800
−76 −76
−65 −65
−63 −64
−55 −55
−82 −86
−78 −85
−73 −83
−67 −76
−157
−157
−155
−154
−166
−162
−158
−157
64 64
62 63
60 61
75 75
74 74
73.5 73.5
69 69
80 80
78 78
74 74
72 72
Unit
MSPS
MSPS
MSPS
ns
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1 Adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9119/AD9129, the minimum interpolation factor is 1.
Thus, with fDAC = 2800 MSPS, fDAC adjusted = 2800 MSPS.
Rev. 0 | Page 6 of 68
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