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PDF AK8451 Data sheet ( Hoja de datos )
| Número de pieza | AK8451 | |
| Descripción | 1 channel-input 16 bit 6MSPS ADC | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK8451]
AK8451
1 channel-input 16 bit 6MSPS ADC
Device Outline
■AFE Block
The AK8451 is a +3.3 V, Two Channel 16 Bit 6MSPS ADC which integrates on-chip Offset
Adjust DAC, Gain Adjust PGA, CDS circuit and <4.5~5.7V> 3 channel LED Drivers.
■ LED Driver Block
This product is the 3 channel LED driver who drives the LED of the anode common in the
constant current. The current to pass for each channel can be adjusted by the external resistance
and the register setting. Also, it has the control pins which turn on or off the current.
Features
■AFE Block
CCD I/F
Number of Channels
1 channel
Range
1.98 Vpp (typ.)
Signal Input Range
0~3.3V @ DC Direct Coupled input mode at AVDD = 3.3 V
Integrated On-chip CDS circuit
Compatible with both Positive and Negative signal polarities
ADC
Maximum Conversion Rate 6 MSPS
Resolution
16 Bit (Straight Binary Code)
Black Level Correction DAC
Correctable Range
± 240 mV (typ.)
Resolution
Gain Adjust
8 Bit
Adjustable Range
0 dB ~ +13.9 dB (typ.) (1.0× ~ 4.9×)
Resolution
6 Bit
Total Performance ( Input ~ Video ADC )
Output Noise
5 LSBs rms (typ.) @ PGA Gain = 0 dB setting
Data Output
2 bit wide or 4bit wide
Power Supplies
Analog part: +3.3V ±5 % / Digital Output part: +3.3V ±0.3V
CPU I/F
3-Wire Serial Interface (Write Only)
Clock, Data are commonly shared with A/D Data Output pins
Power Dissipation
132mW (typ.) with DC Direct Coupled input mode at AVDD= 3.3V
Operating Temperature Range
0 °C ~ +70 °C
Package
28 Pin QFN
Pin pitch: 0.4 mm, Mold size: 4 mm × 4 mm
VREF Output for CCD:
1.1V±100mV。10mAmax.
MS0937-E-01
2011/04
1
Free Datasheet http://www.datasheet4u.com/
1 page  
ASAHI KASEI
Pin Allocation
[AK8451]
SDENB 22
MCLK 23
TSMP 24
RESETB 25
VCOM 26
VRN 27
VRP 28
AK8451VN
Top View
14 LEDG_EN
13 LEDR_EN
12 LED_B
11 LED_G
10 LVSS
9 LVDD
8 LED_R
MS0937-E-01
2011/04
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
ASAHI KASEI
[AK8451]
■ AFE block, Switching characteristics
(AVDD=3.135~3.465V, DRVDD=3.0~3.6V, Ta=0∼70°C , unless otherwise specified)
No. Item
pin min. typ. max. unit Condition
1 MCLK cycle time (T) MCLK
41.6
250 ns mode 1(note 2)
20.8 125 mode 2(note 2)
41.6 250 mode 3(note 2)
2 MCLK H / L width
MCLK
20.8
ns mode 1(note 2)
10.4 mode 2(note 2)
20.8 mode 3(note 2)
3 TSMP setup time
TSMP
5
ns Note 1
(referenced to MCLK↑)
4 TSMP hold time
TSMP
5
ns Note 1
(referenced to MCLK↑)
5 Aperture delay
CISIN
2 ns Data level
(referenced to MCLK↑)
6 Aperture delay
CISIN
2 ns Reference level
(referenced to MCLK↑)
7 TSMP cycle
TSMP
4T
mode 1(note 2)
(MCLK period-unit )
8T mode 2(note 2)
4T mode 3(note 2)
8 Data output delay D0,
At load: 20pF
(referenced to MCLK↑) D1,D2,D3
2
Drivability
25 ns
: normal mode
2
20 ns
: x2 mode
9 Pipeline delay
D0,
6 At 4bit bus
(SMP period-unit ) D1,D2,D3
5
At 2bit bus
10 Reset pulse width
RESETB
50
ns
Note 1) Number of MCLK rising edges during TSMP = H duration is allowed to be 1 to 3 times in
Single Edge, 2bit bus Mode operation, and only a single edge is allowed in the other mode
operation.
Note 2) mode 1 ~ mode 3 explanation
mode 1 : single edge/ 4bit bus mode
mode 2 : single edge/ 2bit bus mode
mode 3 : double edge/ 2bit bus mode
MS0937-E-01
2011/04
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet AK8451.PDF ] | |
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