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IT8511G の電気的特性と機能

IT8511GのメーカーはITEです、この部品の機能は「Embedded Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 IT8511G
部品説明 Embedded Controller
メーカ ITE
ロゴ ITE ロゴ 




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IT8511G Datasheet, IT8511G PDF,ピン配置, 機能
IT8511E/TE/G
Embedded Controller
Preliminary Specification 0.4.1
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
Free Datasheet http://www.datasheet4u.com/

1 Page





IT8511G pdf, ピン配列
Section
7
Revision History
Revision
In section 7.5.4 Alternate Function Selection, the followings were revised:
1. The “output driving” of GPIOB3-4 was revised to “4“.
2. The “output driving” of GPIOC1-2 was revised to “4“ and GPIOE7 was
revised to “4“.
3. GPIOE0-3 don’t support neither “pull-up” nor “pull-down”.
4. The “default pull” of GPIOI7 was revised to “Up“.
Page No.
181
www.ite.com.tw
1 IT8511E/TE/G V0.4.1
Free Datasheet http://www.datasheet4u.com/


3Pages


IT8511G 電子部品, 半導体
Contents
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 58
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 58
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 58
6.2.10.6 I/O Port Base Address Bits [15:8] for Descriptor 2 (IOBAD2[15:8]) ........................ 58
6.2.10.7 I/O Port Base Address Bits [7:0] for Descriptor 2 (IOBAD2[7:0]) ............................ 58
6.2.10.8 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 59
6.2.10.9 Interrupt Request Type Select (IRQTP) .................................................................. 59
6.2.11 Programming Guide ............................................................................................................. 60
6.3 Shared Memory Flash Interface Bridge (SMFI) ................................................................................ 62
6.3.1 Overview............................................................................................................................... 62
6.3.2 Features ............................................................................................................................... 62
6.3.3 Function Description............................................................................................................. 62
6.3.3.1 Supported Flash ...................................................................................................... 62
6.3.3.2 Host to M Bus Translation ....................................................................................... 62
6.3.3.3 Memory Mapping ..................................................................................................... 62
6.3.3.4 Host-Indirect Memory Read/Write Transaction ....................................................... 63
6.3.3.5 EC-Indirect Memory Read/Write Transaction.......................................................... 63
6.3.3.6 Locking Between Host and EC Domains................................................................. 64
6.3.3.7 Host Access Protection............................................................................................ 64
6.3.3.8 Response to a Forbidden Access............................................................................ 64
6.3.3.9 Scratch SRAM ......................................................................................................... 64
6.3.3.10 DMA for Scratch SRAM ........................................................................................... 66
6.3.3.11 Trusted ROM/RAM .................................................................................................. 66
6.3.3.12 Flash Programming via Host LPC Interface with Scratch SRAM............................ 66
6.3.4 EC Interface Registers ......................................................................................................... 67
6.3.4.1 FBIU Configuration Register (FBCFG) .................................................................... 68
6.3.4.2 Flash Programming Configuration Register (FPCFG)............................................. 68
6.3.4.3 Flash EC Code Banking Select Register (FECBSR)............................................... 69
6.3.4.4 Flash Memory Size Select Register (FMSSR) ........................................................ 70
6.3.4.5 Shared Memory EC Control and Status Register (SMECCS)................................. 71
6.3.4.6 Shared Memory Host Semaphore Register (SMHSR) ............................................ 71
6.3.4.7 Shared Memory EC Override Read Protect Registers 0-1 (SMECORPR0-1) ........ 72
6.3.4.8 Shared Memory EC Override Write Protect Registers 0-1 (SMECOWPR0-1) ....... 72
6.3.4.9 Host Control 2 Register (HCTRL2R) ....................................................................... 72
6.3.4.10 Trusted ROM Register (TROMR) ............................................................................ 73
6.3.4.11 EC-Indirect Memory Address Register 0 (ECINDAR0) ........................................... 73
6.3.4.12 EC-Indirect Memory Address Register 1 (ECINDAR1) ........................................... 73
6.3.4.13 EC-Indirect Memory Address Register 2 (ECINDAR2) ........................................... 73
6.3.4.14 EC-Indirect Memory Address Register 3 (ECINDAR3) ........................................... 73
6.3.4.15 EC-Indirect Memory Data Register (ECINDDR)...................................................... 73
6.3.4.16 Scratch SRAM 0 Address Low Byte Register (SCAR0L) ........................................ 74
6.3.4.17 Scratch SRAM 0 Address Middle Byte Register (SCAR0M) ................................... 74
6.3.4.18 Scratch SRAM 0 Address High Byte Register (SCAR0H)....................................... 74
6.3.4.19 Scratch SRAM 1 Address Low Byte Register (SCAR1L) ........................................ 74
6.3.4.20 Scratch SRAM 1 Address Middle Byte Register (SCAR1M) ................................... 74
6.3.4.21 Scratch SRAM 1 Address High Byte Register (SCAR1H)....................................... 74
6.3.4.22 Scratch SRAM 2 Address Low Byte Register (SCAR2L) ........................................ 75
6.3.4.23 Scratch SRAM 2 Address Middle Byte Register (SCAR2M) ................................... 75
6.3.4.24 Scratch SRAM 2 Address High Byte Register (SCAR2H)....................................... 75
6.3.4.25 Scratch SRAM 3 Address Low Byte Register (SCAR3L) ........................................ 75
6.3.4.26 Scratch SRAM 3 Address Middle Byte Register (SCAR3M) ................................... 75
6.3.4.27 Scratch SRAM 3 Address High Byte Register (SCAR3H)....................................... 75
6.3.4.28 Scratch SRAM 4 Address Low Byte Register (SCAR4L) ........................................ 76
6.3.4.29 Scratch SRAM 4 Address Middle Byte Register (SCAR4M) ................................... 76
6.3.4.30 Scratch SRAM 4 Address High Byte Register (SCAR4H)....................................... 76
6.3.5 Host Interface Registers....................................................................................................... 76
www.ite.com.tw
iii IT8511E/TE/G V0.4.1
Free Datasheet http://www.datasheet4u.com/

6 Page



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共有リンク

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部品番号部品説明メーカ
IT8511E

Embedded Controller

ITE
ITE
IT8511G

Embedded Controller

ITE
ITE
IT8511TE

Embedded Controller

ITE
ITE


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