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PDF 23NM60N Data sheet ( Hoja de datos )

Número de pieza 23NM60N
Descripción STB23NM60N
Fabricantes STMicroelectronics 
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No Preview Available ! 23NM60N Hoja de datos, Descripción, Manual

STB23NM60N-STF23NM60N
STI23NM60N-STP23NM60N-STW23NM60N
N-channel 600 V - 0.150 - 19 A - D2PAK - I2PAK - TO-220/FP
TO-247, second generation MDmesh™ Power MOSFET
Features
Type
VDSS
RDS(on)
(@Tjmax) max
ID
STB23NM60N
STI23NM60N
STF23NM60N
STP23NM60N
STW23NM60N
650 V
0.180
19 A
19 A
19 A (1)
19 A
19 A
1. Limited only by maximum temperature allowed
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
Application
Switching applications
Description
This series of devices is designed using the
second generation of MDmesh™ technology. This
revolutionary Power MOSFET associates a new
vertical structure to the company’s strip layout to
yield one of the world’s lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters.
3
1
D²PAK
3
2
1
TO-220
123
I²PAK
3
2
1
TO-247
3
2
1
TO-220FP
Figure 1. Internal schematic diagram
Table 1. Device summary
Order codes
STB23NM60N
STI23NM60N
STF23NM60N
STP23NM60N
STW23NM60N
Marking
23NM60N
23NM60N
23NM60N
23NM60N
23NM60N
Package
D²PAK
I²PAK
TO-220FP
TO-220
TO-247
Packaging
Tape and reel
Tube
Tube
Tube
Tube
March 2008
Rev 3
1/19
www.st.com
19
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23NM60N pdf
STB23NM60N-STF/I23NM60N-STP23NM60N-STW23NM60N
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V(BR)DSS
Drain-source breakdown
voltage
ID = 1 mA, VGS= 0
600
V
dv/dt(1)
Drain-source voltage slope
VDD = 480 V, ID = 19 A,
VGS = 10 V
30 V/ns
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating,@125 °C
1 µA
100 µA
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
100 nA
VGS(th) Gate threshold voltage
VDS= VGS, ID = 250 µA
2 3 4V
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 9.5 A
0.150 0.180
1. Characteristic value at turn off on inductive load
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs(1)
Ciss
Coss
Crss
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =15 V, ID= 9.5 A
VDS = 50 V, f =1 MHz,
VGS = 0
17
2050
140
8
S
pF
pF
pF
Coss
(2)
eq.
Equivalent output
capacitance
VGS = 0, VDS = 0 to 480 V
260
pF
Rg Gate input resistance
f=1 MHz Gate DC Bias=0
Test signal level=20 mV
open drain
4
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 480 V, ID = 19 A
VGS = 10 V
(see Figure 19)
60 nC
10 nC
30 nC
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
5/19
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23NM60N arduino
STB23NM60N-STF/I23NM60N-STP23NM60N-STW23NM60N
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/19
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