DataSheet.jp

IS61NSCS25672 の電気的特性と機能

IS61NSCS25672のメーカーはIntegrated Silicon Solutionです、この部品の機能は「(IS61NSCS25672 / IS61NSCS51236) Synchronous SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61NSCS25672
部品説明 (IS61NSCS25672 / IS61NSCS51236) Synchronous SRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




このページの下部にプレビューとIS61NSCS25672ダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

IS61NSCS25672 Datasheet, IS61NSCS25672 PDF,ピン配置, 機能
IS61NSCS25672
IS61NSCS51236
ΣRAM 256K x 72, 512K x 36
18Mb Synchronous SRAM
ISSI®
ADVANCE INFORMATION
JUNE 2001
Features
• JEDEC SigmaRam pinout and package standard
• Single 1.8V power supply (VCC): 1.7V (min)
to 1.9V (max)
• Dedicated output supply voltage (VCCQ): 1.8V
or 1.5V typical
• LVCMOS-compatible I/O interface
• Common data I/O pins (DQs)
• Single Data Rate (SDR) data transfers
• Pipelined (PL) read operations
• Double Late Write (DLW) write operations
• Burst and non-burst read and write operations,
selectable via dedicated control pin (ADV)
• Internally controlled Linear Burst address
sequencing during burst operations
• Burst length of 2, 3, or 4, with automatic address
wrap
• Full read/write coherency
• Byte write capability
• Two cycle deselect
• Single-ended input clock (CLK)
• Data-referenced output clocks (CQ/CQ)
• Selectable output driver impedance via dedicated
control pin (ZQ)
• Echo clock outputs track data output drivers
• Depth expansion capability (2 or 4 banks) via
programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard
1149.1)
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball
Grid Array (BGA) package
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
SigmaRAM Family Overview
The IS61NSCS series ΣRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
The implementations are 18,874,368-bit (18Mb) SRAMs.
These are the first in a family of wide, very low voltage CMOS
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking
systems.
ISSIs ΣRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs.
The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of
address bursting, output data registering and write cueing.
ΣRAMs allow a user to implement the interface protocol best
suited to the task at hand.
This specific product is Common I/O, SDR, Double Late
Write & Pipelined Read (same as Pipelined NBT) and in
the family is identified as 1x1Dp.
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
1
Free Datasheet http://www.datasheet4u.com/

1 Page





IS61NSCS25672 pdf, ピン配列
IS61NSCS25672
IS61NSCS51236
ISSI ®
IS61NSCS51236 PINOUT
512K x 36 Common I/OTop View
1234
A NC
NC
A
E2
B NC NC Bc NC
C NC NC NC Bd
D NC
NC
E NC DQPc
F DQc
DQc
G DQc
DQc
H DQc
DQc
J DQc
K CQ2
DQc
CQ2
L NC
NC
M NC
NC
N NC
NC
P NC
NC
R DQPd
NC
T DQd DQd
U DQd
DQd
GND
VCCQ
GND
VCCQ
GND
VCCQ
CLK
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
V DQd
DQd
A
A
W DQd
DQd
TMS
TDI
5
A
(16M)
A
(x36)
NC
(128M)
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
VCC
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
VCC
MCL
A
A1
A0
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
7
A
A
NC
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(32M)
A
A
8
E3
Bb
NC
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
A
TDO
9 10 11
A DQb DQb
NC DQb DQb
Ba DQb DQb
GND
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
DQb
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQPa
NC
NC
DQb
DQPb
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
NC
NC
NC
A NC
TCK NC
NC
NC
Integrated Silicon Solution, Inc. 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
3
Free Datasheet http://www.datasheet4u.com/


3Pages


IS61NSCS25672 電子部品, 半導体
IS61NSCS25672
IS61NSCS51236
ISSI ®
BACKGROUND
The central characteristics of the ISSI ΣRAMs are that
they are extremely fast and consume very little power.
Because both operating and interface power is low,
ΣRAMs can be implemented in a wide (x72) configuration,
providing very high single package bandwidth (in excess
of 20 Gb/s in ordinary pipelined configuration) and very low
random access latency (5 ns). The use of very low voltage
circuits in the core and 1.8V or 1.5V interface voltages allow
the speed, power and density performance of ΣRAMs.
Although the SigmaRAM family pinouts have been designed
to support a number of different common read and write
protocol options, not all SigmaRAM implementations will
support all possible protocols. The following timing diagrams
provide a quick comparison between read and write
protocols options available in the context of the SigmaRAM
standard. This data sheet covers the single data rate (non-
DDR), Double Late Write, Pipelined Read SigmaRAM.
The character of the applications for fast synchronous
SRAMs in networking systems are extremely diverse.
ΣRAMs have been developed to address the diverse
needs of the networking market in a manner that can be
supported with a unified development and manufacturing
infrastructure. ΣRAMs address each of the bus protocol
options commonly found in networking systems. This
allows the ΣRAM to find application in radical shrinks and
speed-ups of existing networking chip sets that were
designed for use with older SRAMs, like the NBT or Nt,
Late Write, or Double Data Rate SRAMs, as well as with
new chip sets and ASIC’s that employ the Echo Clocks
and realize the full potential of the ΣRAMs.
COMMON I/O SigmaRAM FAMILY MODE COMPARISONLATE WRITE VS. DOUBLE LATE WRITE
Double Late WritePipelined Read (Σ1x1Dp). For reference only.
CK
Address A
Control R
DQ
CQ
BC
WR
QA
DE
WR
DB QC
F
W
DD QE
Late WritePipelined Read (Σ1x1Lp). For reference only.
CK
Address A
Control R
DQ
CQ
BC DE
XWRX
QA DC
F
W
QD
DF
6 Integrated Silicon Solution, Inc. 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
Free Datasheet http://www.datasheet4u.com/

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ IS61NSCS25672 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IS61NSCS25672

(IS61NSCS25672 / IS61NSCS51236) Synchronous SRAM

Integrated Silicon Solution
Integrated Silicon Solution


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap