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PDF 16N25E Data sheet ( Hoja de datos )
| Número de pieza | 16N25E | |
| Descripción | MTB16N25E | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB16N25E/D
Designer's
™ Data Sheet
TMOS E-FET .™
High Energy Power FET
D 2 PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS E–FET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a drain–to–source diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add –T4
Suffix to Part Number
G
®
D
S
MTB16N25E
Motorola Preferred Device
TMOS POWER FET
16 AMPERES
250 VOLTS
RDS(on) = 0.25 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS 250 Vdc
VDGR 250 Vdc
VGS
± 20 Vdc
VGSM ± 40 Vpk
Drain Current — Continuous
Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID 16 Adc
ID 10
IDM 56 Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
PD 125 Watts
1.0 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25 Ω )
EAS 384 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.0 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
© MMoototororloa,laIncT.M19O95S Power MOSFET Transistor Device Data
1
Free Datasheet http://www.datasheet4u.com/
1 page  
12
9
Q1
6
QT
Q2
200
VGS
150
100
ID = 16 A
3 TJ = 25°C 50
Q3
0
0 10
20 30 40
QT, TOTAL CHARGE (nC)
VDS
50
0
60
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
1000
VDD = 250 V
ID = 16 A
VGS = 10 V
TJ = 25°C
100
tr
td(off)
10 td(on)
MTB16N25E
tf
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
16
VGS = 0 V
TJ = 25°C
12
8
4
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
Free Datasheet http://www.datasheet4u.com/
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 16N25E.PDF ] | |
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