|
|
PDF IS61VF409618B Data sheet ( Hoja de datos )
| Número de pieza | IS61VF409618B | |
| Descripción | 2M x 36 / 4M x 18 / 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS61VF409618B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
2M x 36, 4M x 18
72 Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
ADVANCED INFORMATION
OCTOBER 2012
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LF: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)
VF: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)
VVF: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-
pin PBGA packages
• Lead-free available
DESCRIPTION
The 72Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and network-
ing applications. The IS61LF/VF204836B is organized as
2,096,952 words by 36 bits. The IS61LF/VF409618B is
organized as 4,193,904 words by 18 bits. Fabricated with
ISSI's advanced CMOS technology, the device integrates
a 2-bit burst counter, high-speed SRAM core, and high-
drive capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be writ-
ten. Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol Parameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
-6.5
6.5
7.5
133
-7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. 00B
10/15/2012
Free Datasheet http://www.datasheet4u.com/
1 page  
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
119 BGA PACKAGE PIN CONFIGURATION
4Mx18 (TOP VIEW)
1 2 3 4 5 67
A VDDQ
A
A ADSP A
A VDDQ
B NC
A
A ADSC A
A NC
C NC
A
A VDD A
A NC
D DQb
NC
Vss
NC
Vss DQPa NC
E NC DQb Vss CE Vss NC DQa
F VDDQ
NC
Vss
OE
Vss
DQa
VDDQ
G NC
DQb
BWb
ADV
Vss
NC DQa
H DQb
NC
Vss
GW
Vss
DQa
NC
J VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K NC DQb Vss CLK Vss NC DQa
L DQb
NC
Vss
NC
BWa
DQa
NC
M VDDQ
DQb
Vss BWE Vss
NC VDDQ
N DQb
NC
Vss
A1*
Vss
DQa
NC
P
NC
DQPb
Vss
A0*
Vss
NC DQa
R NC
A
MODE
VDD
NC
A NC
T A A A NC A A ZZ
U VDDQ TMS
TDI
TCK
TDO
NC VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A Synchronous Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Synchronous Address Status Processor
ADSC
Synchronous Address Status Controller
GW Synchronous Global Write Enable
CLK
CE
Synchronous Clock
Synchronous Chip Select
BWa-BWb Synchronous Byte Write Controls
BWE
Synchronous Byte Write Enable
Symbol
Pin Name
OE Asynchronous Output Enable
ZZ Asynchronous Power Sleep Mode
MODE
Synchronous Burst Sequence
Selection
TCK, TDO
JTAG Pins
TMS, TDI
NC No Connect
DQa-DQb
Synchronous Data Inputs/Outputs
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Vdd
Power Supply
Vddq
I/O Power Supply
Vss Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. 00B
10/15/2012
5 Page 
IS61LF204836B, IS61VF/VVF204836B
IS61LF409618B, IS61VF/VVF409618B
POWER UP SEQUENCE
Vddq → Vdd1 → I/O Pins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the
same time as Vddq provided Vih (level of I/O pins) is lower than Vddq.
POWER-UP INITIALIZATION TIMING
VDD
VDDQ
VDD
power > 1ms
Device Initialization
Device ready for
normal operation
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect)
External Address
A1 A0
1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0
A1 A0
A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. 00B
10/15/2012
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS61VF409618B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS61VF409618B | 2M x 36 / 4M x 18 / 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM | ISSI |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |