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UM10601 の電気的特性と機能

UM10601のメーカーはNXP Semiconductorsです、この部品の機能は「LPC800 User manual」です。


製品の詳細 ( Datasheet PDF )

部品番号 UM10601
部品説明 LPC800 User manual
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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UM10601 Datasheet, UM10601 PDF,ピン配置, 機能
UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012
Preliminary user manual
Document information
Info
Keywords
Content
ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
Abstract
LPC800 Preliminary user manual
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datasheet pdf - http://www.DataSheet4U.net/

1 Page





UM10601 pdf, ピン配列
UM10601
Chapter 1: LPC800 Introductory information
Rev. 1.0 — 7 November 2012
Preliminary user manual
1.1 Introduction
The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the UM10601 includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
1.2 Features
System:
ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
Micro Trace Buffer
System tick timer
Memory:
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16 kB on-chip flash programming memory.
4 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot loader software.
Boot ROM API support:
UART drivers
I2C drivers
Power profiles
IAP/ISP
Digital peripherals:
High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to
18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
Pin interrupt generation capability with boolean pattern-matching feature onup to
eightselectable GPIO inputs.
Switch matrix for flexible configuration of each I/O pin function.
State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.
Multiple-channel multi-rate timer for repetitive interrupt generation at up to four
programmable, fixed rates.
Wake-up timer for self-timed wake-up from reduced power modes.
UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
3 of 313
datasheet pdf - http://www.DataSheet4U.net/


3Pages


UM10601 電子部品, 半導体
NXP Semiconductors
1.4 Block diagram
UM10601
Chapter 1: LPC800 Introductory information
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UM10601
Preliminary user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
6 of 313
datasheet pdf - http://www.DataSheet4U.net/

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UM10601

LPC800 User manual

NXP Semiconductors
NXP Semiconductors


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