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IS31IO7328 の電気的特性と機能

IS31IO7328のメーカーはISSIです、この部品の機能は「MULTI-FUNCTION I/O DRIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS31IO7328
部品説明 MULTI-FUNCTION I/O DRIVER
メーカ ISSI
ロゴ ISSI ロゴ 




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IS31IO7328 Datasheet, IS31IO7328 PDF,ピン配置, 機能
IS31IO7328
MULTI-FUNCTION I/O DRIVER
GENERAL DESCRIPTION
The IS31IO7328 2-wire serial-interfaced peripheral
features 8 I/O ports. Ports are divided into four push
pull I/Os and four open-drain I/Os and transition
detection.
Any of the 8 I/O ports can be configured as an input or
an output. All I/O ports configured as inputs are
continuously monitored for state changes (transition
detection). State changes are indicated by the INT_______
output. The interrupt is latched, allowing detection of
transient changes. When the IS31IO7328 is
subsequently read through the serial interface, any
pending interrupt is cleared.
The open-drain outputs are rated to sink 20mA at
0.22V headroom, and are capable of driving LEDs.
________
The RST input clears the serial interface, terminating
any I2C communication to or from the IS31IO7328. The
IS31IO7328 uses two address inputs to allow 2 I2C
slave addresses. The slave address also determines
the power-up logic state for the I/O ports.
January 2012
FEATURES
400kHz I2C serial interface
2.4V to 5.5V operation
4 push-pull I/O ports
4 open-drain I/O ports, rated to 20mA sink current
at 0.22V headroom
Selectable I/O port power-up default logic states
_______
INT output alerts change on inputs
Low 0.3μA (Typ.) standby current
-40°C to +125°C temperature range
APPLICATIONS
Cell phones
Notebooks
SAN/NAS
Satellite radio
Servers
Automotive
TYPICAL APPLICATION CIRCUIT
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Figure 1 Typical Application Circuit
Integrated Silicon Solution, Inc. – www.issi.com
Rev.A, 12/27/2011
1
datasheet pdf - http://www.DataSheet4U.net/

1 Page





IS31IO7328 pdf, ピン配列
IS31IO7328
PIN CONFIGURATION
Package
Pin Configuration (Top View)
QFN-16
AD 1
RST 2
INT 3
VCC 4
12 PP2
11 PP1
10 PP0
9 OD3
PIN DESCRIPTION
No. Pin
1 AD
________
2 RST
_______
3 INT
4 VCC
5,14
6~9
10~13
15
16
GND
OD0~OD3
PP0~PP3
SCL
SDA
Thermal Pad
Description
Address Inputs. Select device slave address with AD.
_________
Reset Input, Active Low. Drive RST low to clear the 2-wire
interface.
_______
Interrupt Output, Active Low. INT is an open-drain output.
Positive Supply Voltage. Bypass VDD to GND with a ceramic
capacitor of at least 1μF.
http://www.DataSheet4U.net/
Ground.
Open-Drain I/O Ports.
CMOS Push-Pull I/O Ports.
I2C-Compatible Serial-Clock Input.
I2C-Compatible Serial-Data I/O.
Connect to GND.
Integrated Silicon Solution, Inc. – www.issi.com
Rev.A, 12/27/2011
3
datasheet pdf - http://www.DataSheet4U.net/


3Pages


IS31IO7328 電子部品, 半導体
IS31IO7328
TIMING CHARACTERISTICS
VCC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VCC = 3.3V, TA = 25°C. (Note 3)
Symbol
Parameter
Condition Min.
Typ.
Max.
fSCL
tBUF
tHD, STA
tSU, STA
tSU, STO
tHD, DAT
tSU, DAT
tLOW
tHIGH
tR
tF
tF, TX
tSP
Cb
tW
t_______
RST
Serial-Clock Frequency
Bus Free Time Between a STOP and a
START Condition
Hold Time (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL Signals,
Receiving
Fall Time of Both SDA and SCL Signals,
Receiving
Fall Time of SDA Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
________
RST Pulse Width
________
RST Rising to START Condition Setup
Time
(Note 4)
(Note 4)
(Note 4)
(Note 5)
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400
1.3
0.6
0.6
0.6
0.9
100
1.3
0.7
20 + 0.1Cb 300
20 + 0.1Cb 300
20 + 0.1Cb 250
50
400
500
1
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
ns
pF
ns
μs
_______
PORT AND INTERRUPT I N T TIMING CHARACTERISTIC
VDD = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VDD = 3.3V, TA = 25°C. (Note 3)
Parameter
Symbol Condition Min. Typ. Max. Unit
Port Output Data Valid
Port Input Setup Time
Port Input Hold Time
————
I N T Input Data Valid Time
————
I N T Reset Delay Time from Acknowledge
tPV CL100pF
tPSU CL100pF 0
tPH CL100pF 4
tIV CL100pF
tIR CL100pF
4 μs
μs
μs
4 μs
4 μs
Note 1: All parameters are tested at TA = 25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the
undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. ISINK 6mA. tR and tF measured between 0.3 × VCC and 0.7× VCC.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Integrated Silicon Solution, Inc. – www.issi.com
Rev.A, 12/27/2011
6
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6 Page



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