PDF IS31IO7326 Data sheet ( Hoja de datos )

Número de pieza	IS31IO7326
Descripción	DEBOUNCED 8 X 8 KEY-SCAN CONTROLLER
Fabricantes	ISSI
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No Preview Available ! IS31IO7326 DEBOUNCED 8×8 KEY-SCAN CONTROLLER January 2012 GENERAL DESCRIPTION The IS31IO7326 is a 64 key, key-scan controller. It offloads the burden of keyboard scanning from the host processor. The IS31IO7326 supports keypad matrix of up to 8×8. Key press and release events are encoded into a byte format and loaded into a key event register for retrieval by the host processor. The IS31IO7326 integrates a debounce function which rejects false or transient key switch activities. The _______ interrupt output (INT) is used to signify if there are any keypad activities. To minimize power, the IS31IO7326 automatically enters a low power standby mode when there is no keypad, I/O, or host activity. The IS31IO7326 is available in a Pb-free 4mm × 4mm QFN-24 package. FEATURES  2.4V to 5.5V operation  400kHz I2C serial interface  Available for multi-key press detect  Low 0.3μA (typ.) standby current  Operate in -40°C to +125°C  Pb-free 4mm × 4mm QFN-24 package APPLICATIONS  Keypad of QWERTY type phones  PDAs, games, and other handheld applications TYPICAL APPLICATION CIRCUIT VBattery 100k Micro Controller VBattery 1F VDD 4.7k 4.7k 4.7k 100k 21 VCC 0.1 F http://www.DataSheet4U.net/ PP0 PP1 PP2 PP3 PP4 PP5 19 PP6 SCL 20 PP7 22 SDA IS31IO7326 INT OD0 23 RST OD1 OD2 OD3 18 AD0 24 AD1 9 GND OD4 OD5 OD6 OD7 1 2 3 4 14 15 16 17 5 6 7 8 10 11 12 13 Figure 1 Typical Application Circuit Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 1 datasheet pdf - http://www.DataSheet4U.net/ 1 page IS31IO7326 TIMING CHARACTERISTICS TA = -40°C ~ +125°C, VCC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at TA = 25°C, VCC = 3.3V. (Note 3) Symbol Parameter Condition Min. Typ. Max. Units fSCL tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tR tF tF, TX tSP Cb tW t________ RST Serial-clock frequency Bus free time between a STOP and a START condition Hold time (repeated) START condition Repeated START condition setup time STOP condition setup time Data hold time Data setup time SCL clock low period SCL clock high period Rise time of both SDA and SCL signals, receiving Fall time of both SDA and SCL signals, receiving Fall time of SDA transmitting Pulse width of spike suppressed Capacitive load for each bus line ________ RST pulse width ________ RST rising to START condition setup time (Note 3) (Note 4) (Note 4) (Note 4) (Note 5) http://www.DataSheet4U.net/ 400 1.3 0.6 0.6 0.6 0.9 100 1.3 0.7 20 + 0.1Cb 300 20 + 0.1Cb 300 20 + 0.1Cb 250 50 400 500 1 kHz μs μs μs μs μs ns μs μs ns ns ns ns pF ns μs PORT AND INTERRUPT TIMING CHARACTERISTICS T = -40°C ~ +125°C, VCC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at TA = 25°C, VCC = 3.3V (Note 3) Symbol Parameter Condition Min. Typ. Max. Untis tPV Port output data valid CL≤ 100pF 4 μs tPSU Port input setup time CL≤ 100pF 0 μs tPH Port input hold time CL≤ 100pF 4 μs tIV _______ INT input data valid time CL≤ 100pF 4 μs tIR INT_______ reset delay time from acknowledge CL≤ 100pF 4 μs Note 1: All parameters are tested at TA = 25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7× VCC. Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 5 datasheet pdf - http://www.DataSheet4U.net/ 5 Page IS31IO7326 the programmed time. However the temporary key status registers will remain unchanged and the key event data may continue to be read until another key event is detected. After all of the key events have been read, the device returns to standby mode waiting for the next scan. _______ AUTO-CLEAR INT FUNCTION When the ACI bits of the Configuration Register (08h) are set to “01” or “10”, this function is enabled. Setting the ACI bits to “00” disables the function. When enabled, the INT_______ would be cleared in 5ms or 10ms after it asserts if there is no read of the Key Status Register. The data in the temporary key status _______ registers does not change when the INT goes low. The Key Status Register can be read regardless of whether _______ _______ the INT is high or not. However, when the INT is cleared and there is new key event activity before the old key event data is read, the temporary key status registers are rewritten and the INT_______ asserts again. In this case, the previous key event data is lost and only the new key event(s) can be read. THE INPUT PORT FILTER The bit DE of the Configuration Register (08h) is used to enable the input port filter. When DE is set to “0”, the input port filter is disabled, and the chip responds to any changes at the input port. When DE is set to “1”, the input port filter is enabled and any glitch shorter than 100ns is filtered. If the input pulse width is greater than 100ns, the chip responds (Figure 10). Figure 10 Input port debounce function http://www.DataSheet4U.net/ Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/19/2011 11 datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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