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PDF BU-61582 Data sheet ( Hoja de datos )
| Número de pieza | BU-61582 | |
| Descripción | SPACE LEVEL MIL-STD-1553 BC/RT/MT | |
| Fabricantes | DDC | |
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BU-61582
SPACE LEVEL MIL-STD-1553 BC/RT/MT
ADVANCED COMMUNICATION
ENGINE (SP’ACE) TERMINAL
DESCRIPTION
DDC’s BU-61582 Space Advanced Communication Engine (SP’ACE)
is a radiation hardened version of the BU-61580 ACE terminal. DDC
supplies the BU-61582 with enhanced screening for space and other
high reliability applications.
The BU-61582 provides a complete integrated BC/RT/MT interfacehttp://www.DataSheet4U.net/
between a host processor and a MIL-STD-1553 bus. The BU-61582
maintains functional and software compatibility with the standard BU-
61580 product and is packaged in the same 1.9 square-inch package
footprint.
As an option, DDC can supply the BU-61582 with space level screen-
ing. This entails enhancements in the areas of element evaluation and
screening procedures for active and passive elements, as well as the
manufacturing and screening processes used in producing the termi-
nals.
The BU-61582 integrates dual transceiver, protocol, memory man-
agement and processor interface logic, and 16K words of RAM in the
choice of 70-pin DIP or flat pack packages. Transceiverless versions
may be used with an external electrical or fiber optic transceiver.
To minimize board space and ‘glue’ logic, the SP’ACE terminals pro-
vide ultimate flexibility in interfacing to a host processor and inter-
nal/external RAM.
Make sure the next
Card you purchase
has...
®
FEATURES
• Radiation-Hardened to 1 MRad
• Fully Integrated 1553 Terminal
• Flexible Processor Interface
• 16K x 16 Internal RAM
• Automatic BC Retries
• Programmable BC Gap Times
• BC Frame Auto-Repeat
• Intelligent RT Data Buffering
• Small Ceramic Package
• Available to SMD 5962-96887
• Multiple Ordering Options;
+5V (Only)
+5V/-15V
+5V/-12V
+5V/Transceiverless
+5V (Only, with Transmit Inhibits)
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
© 1998, 1999 Data Device Corporation
datasheet pdf - http://www.DataSheet4U.net/
1 page  
FUNCTIONAL OVERVIEW
TRANSCEIVERS
For the +5 V and -15 V/-12 V front end, the BU-61582X1(X2)
uses low-power bipolar analog monolithic and thin-film hybrid
technology. The transceiver requires +5 V and -15 V (-12 V) only
(requiring no +15 V/+12 V) and includes voltage source trans-
mitters. The voltage source transmitters provide superior line
driving capability for long cables and heavy amounts of bus load-
ing.
The receiver sections of the BU-61582 are fully compliant
with MIL-STD-1553B in terms of front end overvoltage pro-
tection, threshold, common mode rejection, and word error
rate. In addition, the receiver filters have been designed for
optimal operation with the J-Rad chip’s Manchester II
decoders.
J-RAD DIGITAL MONOLITHIC
The J-Rad digital monolithic represents the cornerstone element
of the BU-61582 SP’ACE family of terminals. The J-Rad chip is
actually a radiation hardened version of DDC’s J’ (J-prime)
monolithic which is the key building block behind DDC’s non-radi-
ation hardened BU-61580 ACE series of terminals. As such, the
J-Rad possesses all the enhanced hardware and software fea-
tures which have made the BU-61580 ACE the industry standard
1553 interface component.
The J-Rad chip consists of a dual encoder/decoder, complete
protocol for Bus Controller (BC), 1553A/B/McAir Remote
Terminal (RT), and Monitor (MT) modes; memory management
and interrupt logic; a flexible, buffered interface to a host proces-
sor bus and optional external RAM; and a separate buffered
interface to external RAM. Reference the region within the dotted
line of FIGURE 1. Besides realizing all the protocol, memory
management, and interface functions of the earlier AIM-HY
series, the J-Rad chip includes a large number of enhancements
to facilitate hardware and software design, and to further off-load
the 1553 terminal’s host processor.
DECODERS
The default mode of operation for the BU-61582 BC/RT/MT
requires a 16 MHz clock input. If needed, a software program-
mable option allows the device to be operated from a 12 MHz
clock input. Most current 1553 decoders sample using a 10 MHz
or 12 MHz clock. In the 16 MHz mode (default following a hard-
ware or software reset), the decoders sample 1553 serial data
using the 16 MHz clock. In the 12 MHz mode (or 16 MHz), the
decoders can be programmed to sample using both clock edges;
this provides a sampling rate of 24 MHz. The faster sampling rate
for the J-Rad’s Manchester II decoders provides superior per-
formance in terms of bit error rate and zero-crossing distortion
tolerance.
For interfacing to fiber optic transceivers for MIL-STD-1773
applications, a transceiverless version of the SP’ACE can be
used. These versions provide a register programmable option for
a direct interface to the single-ended outputs of a fiber optic
receiver. No external logic is needed.
TIME TAGGING
The SP’ACE includes an internal read/writable Time Tag
Register. This register is a CPU read/writable 16-bit counter with
a programmable resolution of either 2, 4, 8, 16, 32, or 64 µs per
LSB. Also, the Time Tag Register may be clocked from an exter-
nal oscillator. Another option allows software controlled incre-
menting of the Time Tag Register. This supports self-test for the
Time Tag Register. For each message processed, the value of
the Time Tag register is loaded into the second location of the
respective descriptor stack entry (“TIME TAG WORD”) for both
BC and RT modes.
Additional provided options will: clear the Time Tag Register fol-
lowing a Synchronize (without data) mode command or load the
Time Tag Register following a Synchronize (with data) mode
command; enable an interrupt request and a bit setting in the
Interrupt Status Register when the Time Tag Register rolls over
from FFFF to 0000. Assuming the Time Tag Register is not
loaded or reset, this will occur at approximately 4 second time
intervals, for 64 µs/LSB resolution, down to 131 ms intervals,
for 2 µs/LSB resolution.
Another programmable option for RT mode is the automatic clear-
http://www.DataSheet4U.net/
ing of the Service Request Status Word bit following the
BU-61582’s response to a Transmit Vector Word mode command.
INTERRUPTS
The SP’ACE series components provide many programmable
options for interrupt generation and handling. The interrupt out-
put pin INT has three software programmable modes of opera-
tion: a pulse, a level output cleared under software control, or a
level output automatically cleared following a read of the
Interrupt Status Register. Individual interrupts are enabled by the
Interrupt Mask Register. The host processor may easily deter-
mine the cause of the interrupt by using the Interrupt Status
Register. The Interrupt Status Register provides the current state
of the interrupt conditions. The Interrupt Status Register may be
updated in two ways. In the standard interrupt handling mode, a
particular bit in the Interrupt Status Register will be updated only
if the condition exists and the corresponding bit in the Interrupt
Mask Register is enabled. In the enhanced interrupt handling
mode, a particular bit in the Interrupt Status Register will be
updated if the condition exists regardless of the contents of the
corresponding Interrupt Mask Register bit. In any case, the
respective Interrupt Mask Register bit enables an interrupt for a
particular condition.
Data Device Corporation
www.ddc-web.com
5
BU-61582
M-08/04-0
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
TABLE 15. CONFIGURATION REGISTER #4
(READ/WRITE 08H)
BIT DESCRIPTION
15(MSB) EXTERNAL BIT WORD ENABLE
14 INHIBIT BIT WORD IF BUSY
13 MODE COMMAND OVERRIDE BUSY
12 EXPANDED BC CONTROL WORD ENABLE
11 BROADCAST MASK ENABLE/XOR
10 RETRY IF -A AND M.E.
9 RETRY IF STATUS SET
8 1ST RETRY ALT/SAME BUS
7 2ND RETRY ALT/SAME BUS
6 VALID M.E./NO DATA
5 VALID BUSY/NO DATA
4 MT TAG GAP OPTION
3 LATCH RT ADDRESS WITH CONFIG #5
2 TEST MODE 2
1 TEST MODE 1
0(LSB) TEST MODE 0
TABLE 16. CONFIGURATION REGISTER #5
(READ/WRITE 09H)
BIT DESCRIPTION
15(MSB) 12MHZ CLOCK SELECT
14 SINGLE ENDED SELECT
13 EXTERNAL TX INHIBIT A, read only
12 EXTERNAL TX INHIBIT B, read only
11 EXPANDED CROSSING ENABLED
10 RESPONSE TIMEOUT SELECT 1
9 RESPONSE TIMEOUT SELECT 0
8 GAP CHECK ENABLED
7 BROADCAST DISABLED
6 RT ADDRESS LATCH/TRANSPARENT (see Note)
5 RT ADDRESS 4
4 RT ADDRESS 3
3 RT ADDRESS 2
2 RT ADDRESS 1
1 RT ADDRESS 0
0(LSB) RT ADDRESS PARITY
Note: Read only, logic “0” for 61582, logic “1” for 61583.
TABLE 17. MONITOR DATA STACK ADDRESS
REGISTER (READ/WRITE 0AH)
BIT DESCRIPTION
15(MSB) MONITOR DATA STACK ADDRESS 15
••
••
••
0(LSB) MONITOR DATA STACK ADDRESS 0
Data Device Corporation
www.ddc-web.com
TABLE 18. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH)
BIT DESCRIPTION
15(MSB) BC FRAME TIME REMAINING 15
••
••
••
0(LSB) BC FRAME TIME REMAINING 0
Note: resolution 100 µs per LSB
TABLE 19. BC MESSAGE TIME REMAINING
REGISTER (READ/WRITE 0CH)
BIT DESCRIPTION
15(MSB) BC MESSAGE TIME REMAINING 15
••
••
••
0(LSB) BC MESSAGE TIME REMAINING 0
Note: resolution = 1 µs per LSB
TABLE 20. BC FRAME TIME/RT LAST COMMAND/
TRIGGER REGISTER (READ/WRITE 0DH)
BIT DESCRIPTION
15(MSB) BIT 15
••
•http://www.DataSheet4U.net/
•
••
0(LSB) BIT 0
TABLE 21. RT STATUS WORD REGISTER
(READ/WRITE 0EH)
BIT DESCRIPTION
15(MSB) LOGIC “0”
14 LOGIC “0”
13 LOGIC “0”
12 LOGIC “0”
11 LOGIC “0”
10 MESSAGE ERROR
9 INSTRUMENTATION
8 SERVICE REQUEST
7 RESERVED
6 RESERVED
5 RESERVED
4 BROADCAST COMMAND RECEIVED
3 BUSY
2 SUBSYSTEM FLAG
1 DYNAMIC BUS CONTROL ACCEPT
0(LSB) TERMINAL FLAG
BU-61582
11 M-08/04-0
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BU-61582.PDF ] | |
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