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BU-61581 の電気的特性と機能

BU-61581のメーカーはDDCです、この部品の機能は「(BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT」です。


製品の詳細 ( Datasheet PDF )

部品番号 BU-61581
部品説明 (BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT
メーカ DDC
ロゴ DDC ロゴ 




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BU-61581 Datasheet, BU-61581 PDF,ピン配置, 機能
BU-65170/61580 and BU-61585
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
ACE User’s Guide
Also Available
DESCRIPTION
DDC's BU-65170, BU-61580 and
BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal
(BC/RT/MT)
Advanced
Communication Engine (ACE) termi-
nals comprise a complete integrated
interface between a host processor
and a MIL-STD-1553 A and B or
STANAG 3838 bus.
configured as 12K x 16 or 8K x 17.
The 8K x 17 RAM feature provides
capability for memory integrity check-
ing by implementing RAM parity gen-
eration and verification on all access-
es. To minimize board space and
“glue” logic, the ACE provides ultimate
flexibility in interfacing to a host
processor and internal/external RAM.
The ACE series is packaged in a 1.9 -
square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM)
ceramic package that is well suited for
applications with stringent height
requirements.
The BU-61585 ACE integrates dual
transceiver, protocol, memory man-
agement, processor interface logic,
and a total of 12K words of RAM in a
choice of DIP or flat pack packages.
The BU-61585 requires +5 V power
and either -15 V or -12 V power.
The BU-61585 internal RAM can be
The advanced functional architecture
of the ACE terminals provides soft-
ware compatibility to DDC's
Advanced Integrated Multiplexer (AIM)
series hybrids, while incorporating a
multiplicity of architectural enhance-
ments. It allows flexible operation
while off-loading the host processor,
ensuring data sample consistency,
and supports bulk data transfers.
The ACE hybrids may be operated at
either 12 or 16 MHz. Wire bond
options allow for programmable RThttp://www.DataSheet4U.net/
address (hardwired is standard) and
external transmitter inhibit inputs.
FEATURES
Fully Integrated MIL-STD-1553
Interface Terminal
Flexible Processor/Memory
Interface
Standard 4K x 16 RAM and
Optional 12K x 16 or 8K x 17 RAM
Available
Optional RAM Parity
Generation/Checking
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Flexible RT Data Buffering
Programmable Illegalization
Selective Message Monitor
Simultaneous RT/Monitor Mode
CH. A
TX/RX_A
TRANSCEIVER
A
TX/RX_A
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
*SHARED
RAM
DATA BUS
ADDRESS BUS
DATA
BUFFERS
ADDRESS
BUFFERS
D15-D0
A15-A0
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
RT ADDRESS
MISCELLANEOUS
TX/RX_B
RTAD4-RTAD0, RTADP
INCMD
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
PROCESSOR
AND
MEMORY
CONTROL
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
INT INTERRUPT
REQUEST
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ACE BLOCK DIAGRAM
© 1992, 1999 Data Device Corporation
datasheet pdf - http://www.DataSheet4U.net/

1 Page





BU-61581 pdf, ピン配列
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
PARAMETER
MIN TYP MAX UNITS
! BU-61585X2
• +5V (Logic, Ch. A, Ch. B)
• -12V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-61585X3,
BU-61585X6
• +5V (Logic, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
105 240
30 60
80 120
130 185
230 305
mA
mA
mA
mA
mA
105 250
255 400
370 550
600 850
mA
mA
mA
mA
POWER DISSIPATION
Total Hybrid
! BU-65170/61580X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-65170/61580X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-65170/61580X3,
BU-65170/61580X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-61585X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-61585X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-61585X3,
BU-61585X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
! BU-65170/61580X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-65170/61580X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-65170/61580X3,
BU-65170/61580X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
0.850
1.195
1.450
1.975
1.85
2.25
2.72
3.52
0.835
1.135
1.435
2.035
1.67
2.10
2.59
3.46
W
W
W
W
W
W
W
W
0.475
0.905
1.160
1.670
1.00
1.43
1.86
2.72
0.900
1.245
1.500
2.025
2.10
2.50
2.97
3.77
0.885
1.185
1.485
2.085
1.92
2.35
2.84
3.71
W
W
W
W
W
W
W
W
W
W
W
W
0.525
0.955
1.210
1.720
1.25
1.68
2.11
2.97
W
W
W
W
0.335
0.600
0.860
1.385
0.68
1.06
1.45
2.23
0.290
0.590
0.890
1.490
0.59
0.92
1.36
2.16
W
W
W
W
W
W
W
W
0.200
0.630
0.885
1.395
0.25
0.68
1.11
1.97
W
W
W
W
TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)
PARAMETER
! BU-61585X1
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-61585X2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
! BU-61585X3,
BU-61585X6
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN TYP MAX UNITS
0.335
0.600
0.860
1.385
0.68
1.06
1.45
2.23
0.290
0.590
0.890
1.490
0.59
0.92
1.36
2.16
W
W
W
W
W
W
W
W
0.200
0.630
0.885
1.395
0.25
0.68
1.11
1.97
W
W
W
W
CLOCK INPUT
Frequency
! Nominal Value (programmable)
• Default Mode
• Software Programmable Option
! Long Term Tolerance
• 1553A Mode
• 1553B Mode
! Short Term Tolerance, 1 second
• 1553A Mode
• 1553B Mode
! Duty Cycle
• 16 MHz
• 12 MHz
16.0 MHz
12.0 MHz
0.01 %
0.1 %
0.001 %
0.01 %
33 67 %
40 60 %
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-
to-Start of Next Message
http://www.DataSheet4U.net/
BC Intermessage Gap (Note 8)
BC/RT/MT Response Timeout (Note 9)
! 18.5 nominal
! 22.5 nominal
! 50.5 nominal
! 128.0 nominal
RT Response Timeout (Note 11)
Transmitter Watchdog Timeout
2.5
9.5
17.5 18.5
21.5 22.5
49.5 50.5
127 129.5
4
668
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
µs
µs
THERMAL
Thermal Resistance, Junction-to-Case,
Hottest Die (θJC)
! BU-65170/61580/61585X1,
BU-65170/61580/61585X2,
! BU-65170/61580/61585X3,
BU-65170/61580/61585X6
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
-55
-65
6.99 °C/W
6.8 °C/W
150
150
+300
°C
°C
°C
PHYSICAL CHARACTERISTICS
Size
! BU-65170/61580/61585 S
! BU-65170/61580/61585 V
Weight
! BU-65170/61580/61585 S/V
1.9 X 1.0 X 0.165
(48.3 x 25.4 x 4.19)
1.9 X 1.0 X 0.150
(48.3 x 25.4 x 3.81)
in.
(mm)
in.
(mm)
0.6 (17)
oz (g)
Data Device Corporation
www.ddc-web.com
3
BU-65170/61580/61585
H1 web-09/02-0
datasheet pdf - http://www.DataSheet4U.net/


3Pages


BU-61581 電子部品, 半導体
TABLE 2. ADDRESS MAPPING
ADDRESS LINES
REGISTER
DESCRIPTION/ACCESSIBILITY
HEX A4 A3 A2 A1 A0
00 0 0 0 0 0 Interrupt Mask Register (RD/WR)
01 0 0 0 0 1 Configuration Register #1 (RD/WR)
02 0 0 0 1 0 Configuration Register #2 (RD/WR)
03 0 0 0 1 1 Start/Reset Register (WR)
03
0
0
0
1
1
BC/RT Command Stack Pointer Register
(RD)
04
0
0
1
0
0
BC Control Word*/RT Subaddress Control
Word Register (RD/WR)
05 0 0 1 0 1 Time Tag Register (RD/WR)
06 0 0 1 1 0 Interrupt Status Register (RD)
07 0 0 1 1 1 Configuration Register #3 (RD/WR)
08 0 1 0 0 0 Configuration Register #4 (RD/WR)
09 0 1 0 0 1 Configuration Register #5 (RD/WR)
0A 0 1 0 1 0 Data Stack Address Register (RD)*
0B 0 1 0 1 1 BC Frame Time Remaining Register (RD)*
0C
0
1
1
0
0
BC Time Remaining to Next Message
Register (RD)*
0D
0
1
1
0
1
BC Frame Time*/RT Last Command/MT
Trigger Word* Register (RD/WR)
0E 0 1 1 1 0 RT Status Word Register (RD)
0F 0 1 1 1 1 RT BIT Word Register (RD)
10 1 0 0 0 0 Test Mode Register 0
17 1 0 1 1 1 Test Mode Register 7
18 1 1 0 0 0 reserved
1F 1 1 1 1 1 reserved
* Not applicable to BU-65170/61571
Time Tag Register maintains the value of a real-time clock. The resolu-
tion of this register is programmable from among 2, 4, 8, 16, 32, and 64
µs/LSB.The TAG_CLK input signal also may cause an external oscillator
to clock the Time Tag Register. Start-of-Message (SOM) and End-of-
Message (EOM) sequences in BC, RT, and Message Monitor modes
cause a write of the current value of the Time Tag Register to the stack
area of RAM.
Interrupt Status Register mirrors the Interrupt Mask Register and con-
tains a Master Interrupt bit. It allows the host processor to determine the
cause of an interrupt request by means of a single READ operation.
Configuration Registers #3, #4, and #5 are used to enable many of the
BU-61580's advanced features. These include all the enhanced mode
features; that is, all the functionality beyond that of the previous generation
product, the BUS-61559 Advanced Integrated Mux Hybrid with Enhanced
RT Features (AIM-HY'er).For all three modes, use of the Enhanced Mode
enables the various read-only bits in Configuration Register #1. For BC
mode, the enhanced mode features include the expanded BC Control
Word and BC Block Status Word, additional Stop-On-Error and Stop-On-
Status Set functions, frame auto-repeat, programmable intermessage
gap times, automatic retries, expanded Status Word Masking, and the
capability to generate interrupts following the completion of any selected
message. For RT mode, the enhanced mode features include the
expanded RT Block Status Word, the combined RT/Selective Message
Monitor mode, internal wrapping of the RTFAIL output signal (from the J´
chip) to the RTFLAG RT Status Word bit, the double buffering scheme for
individual receive (broadcast) subaddresses, and the alternate (fully soft-
ware programmable) RT Status Word. For MT mode, use of the
enhanced mode enables use of the Selective Message Monitor, the com-
bined RT/Selective Monitor modes, and the monitor triggering capability.
Data Stack Address Register is used to point to the current address
location in shared RAM used for storing message words (second
Command Words, Data Words, RT Status Words) in the Selective Word
Monitor mode.
FrameTime Remaining Register provides a read only indication of the
time remaining in the current BC frame. The resolution of this register is
100 µs/LSB.
Message Time Remaining Register provides a read only indication of
the time remaining before the start of the next message in a BC frame.
The resolution of this register is 1 µs/LSB.
BC Frame/RT Last Command/MT Trigger Word Register: In BC
mode, it programs the BC frame time, for use in the frame auto-repeat
mode. The resolution of this register is 100 µs/LSB, with a range of 6.55
seconds; in RT mode, this register stores the current (or most previous)
1553 Command Word processed by the ACE RT; in the Word Monitor
mode, this register specifies a 16-bit Trigger (Command) Word. The
TriggerWord may be used to start or stop the monitor, or to generate inter-
http://www.DataSheet4U.net/
rupts.
Status Word Register and BIT Word Registers provide read-only indi-
cations of the BU-65170/61580's RT Status and BIT Words.
Test Mode Registers 0-7: These registers may be used to facilitate pro-
duction or maintenance testing of the BU-65170/61580 and systems
incorporating the BU-65170/61580.
TABLE 3. INTERRUPT MASK REGISTER (READ/WRITE 00h)
BIT DESCRIPTION
15(MSB) RESERVED
14 RAM PARITY ERROR
13 BC/RT TRANSMITTER TIMEOUT
12 BC/RT COMMAND STACK ROLLOVER
11 MT COMMAND STACK ROLLOVER
10 MT DATA STACK ROLLOVER
9 HS FAIL
8 BC RETRY
7 RT ADDRESS PARITY ERROR
6 TIME TAG ROLLOVER
5 RT CIRCULAR BUFFER ROLLOVER
4 BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
3 BC END OF FRAME
2 FORMAT ERROR
1 BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
0(LSB) END OF MESSAGE
Data Device Corporation
www.ddc-web.com
6
BU-65170/61580/61585
H1 web-09/02-0
datasheet pdf - http://www.DataSheet4U.net/

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
BU-61580

(BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT

DDC
DDC
BU-61581

(BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT

DDC
DDC
BU-61582

SPACE LEVEL MIL-STD-1553 BC/RT/MT

DDC
DDC
BU-61585

(BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT

DDC
DDC


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